About x86-64.net

x86-64.net explains the x86-64 microarchitecture levels, lists which processors reach them, and shows how to check a machine. It is not affiliated with Intel, AMD, Hygon, Zhaoxin or any operating system vendor; product names are trademarks of their owners.

Where the data comes from#

Level definitions

The x86-64 psABI, which defines the levels.

Feature sets of microarchitectures

GCC’s -march definitions, pinned to a specific commit. The vendors' own compiler engineers maintain them, and they are what -march=<cpu> actually enables. Where GCC has no separate -march (Penryn, Kaby Lake, Zen+ and a few others) the entry says which one applies.

CPUID bits and Linux flag names

The Linux kernel’s cpufeatures.h; AVX10 and APX follow GCC’s cpuid.h.

Models that differ from their microarchitecture

Recorded as exceptions, each with its own source.

Operating system and software requirements

The vendor’s own statement wherever one exists, with the date it was last checked.

Instruction forms, encodings, CPUID bits and processor lists

Intel XED, the encoder and decoder library that Intel publishes under the Apache License 2.0, pinned to a release (see below). The summaries and explanations on those pages are our own, checked against Intel’s manuals and specifications, which each page cites.

C intrinsics

The x86 intrinsic headers of Clang, part of the LLVM Project and licensed under the Apache License 2.0 with LLVM Exceptions, pinned to a release (see below). Every intrinsic is compiled with the Clang of that release to confirm the instruction it compiles to.

Every entry lists its sources on its page. Levels are never typed in: one implementation computes them from the feature sets, and tests pin the result for every microarchitecture, so a change to the data that changes an answer cannot go unnoticed.

The instruction reference#

The instruction and extension pages are generated from Intel XED v2026.08.23 (commit 0bcb6237345c). XED is built from its source code and its own tools export the tables; our build converts them into the tables on the pages without editing the data:

• every form of a mnemonic is one row, with syntax and encoding written in the notation of Intel’s manuals;
• XED’s variants of an instruction with a LOCK or REP prefix appear on the page of the instruction, and instructions that differ only in a condition code share a page;
• processor lists follow XED’s chip model, which covers Intel processors up to Nova Lake and Diamond Rapids and AMD processors up to Zen 2. Where it disagrees with the GCC-based data of the CPU pages, the pages say so.

XED is Copyright Intel Corporation and licensed under the Apache License 2.0, whose terms apply to the tables derived from it; the text of the pages is our own and licensed under CC BY 4.0.

The intrinsics on the instruction pages and the A–Z index come from the x86 headers of Clang 23.1.2 (commit 85ac56026243). Each one is compiled with that Clang and the machine code is decoded with XED, and an intrinsic is listed only where that confirms a single instruction, and the instruction its doc comment names, if any. The index explains the method. The headers are part of the LLVM Project and licensed under the Apache License 2.0 with LLVM Exceptions; the lists of intrinsics and their signatures are derived from them. Intel’s Intrinsics Guide is not used. Nothing is copied from Intel’s instruction set manuals, whose terms do not allow it: every sentence is written in our own words.

Reusing the data#

The complete dataset (features, levels, microarchitectures, exceptions, requirements and sources) can be downloaded as x86.json.

The text and data of this site are licensed under CC BY 4.0: you may copy and adapt them, including commercially, as long as you credit x86-64.net with a link. Code, such as the x86-64-level script, is licensed under the MIT license. The fonts are Inter and Fira Mono, under the SIL Open Font License.

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