About x86-64.net

x86-64.net explains the x86-64 microarchitecture levels, lists which processors reach them, and shows how to check a machine. It is not affiliated with Intel, AMD, Hygon, Zhaoxin or any operating system vendor; product names are trademarks of their owners.

Where the data comes from#

Level definitions

The x86-64 psABI, which defines the levels.

Feature sets of microarchitectures

GCC’s -march definitions, pinned to a specific commit. The vendors' own compiler engineers maintain them, and they are what -march=<cpu> actually enables. Where GCC has no separate -march (Penryn, Kaby Lake, Zen+ and a few others) the entry says which one applies. AMD’s RDPRU, MCOMMIT, INVLPGB and SEV-SNP, which no -march enables, come from AMD’s Processor Programming References, which give the CPUID bits of each processor; each entry cites the references it relies on. Where an entry follows Intel’s own tables rather than GCC (AES-NI on Westmere to Broadwell), its notes say so.

CPUID bits and Linux flag names

The Linux kernel’s cpufeatures.h; AVX10 and APX follow GCC’s cpuid.h.

Models that differ from their microarchitecture

Recorded as exceptions, each with its own source.

Operating system and software requirements

The vendor’s own statement wherever one exists, with the date it was last checked.

Instruction forms, encodings, operands, flags, CPUID bits and processor lists

Intel XED, the encoder and decoder library that Intel publishes under the Apache License 2.0, pinned to a release (see below); AMD’s processors after Zen 2 come from the feature sets above. The summaries and explanations on those pages are our own, checked against Intel’s manuals and specifications, which each page cites.

C intrinsics

The x86 intrinsic headers of Clang, part of the LLVM Project and licensed under the Apache License 2.0 with LLVM Exceptions, pinned to a release (see below). Every intrinsic is compiled with the Clang of that release to confirm the instruction it compiles to.

Every entry lists its sources on its page. Levels are never typed in: one implementation computes them from the feature sets, and tests pin the result for every microarchitecture, so a change to the data that changes an answer cannot go unnoticed.

The instruction reference#

The instruction and extension pages are generated from Intel XED v2026.08.23 (commit 0bcb6237345c). XED is built from its source code and its own tools export the tables; our build converts them into the tables on the pages:

• every form of a mnemonic is one row, with syntax and encoding written in the notation of Intel’s manuals;
• what the forms read and write, the flags they test and change, their exception classes and some of XED’s attributes follow the table, each stated once for all the forms that share it. Where Intel’s documentation describes the flags otherwise, a note under their table says how, and the table keeps XED’s data;
• XED’s variants of an instruction with a LOCK or REP prefix appear on the page of the instruction, and instructions that differ only in a condition code share a page;
• processor lists follow XED’s chip model, which covers Intel processors up to Nova Lake and Diamond Rapids and AMD processors up to Zen 2. AMD’s Zen 3 to Zen 6 follow the CPU data of this site: an ISA set that their features decide (GCC’s -march sets and AMD’s Processor Programming References) follows the features, and the rest, the base instruction set among them, comes from XED’s Zen 2 and from AMD’s references. Where XED’s model disagrees with the CPU data and where only the EPYC processors of a microarchitecture have an ISA set, the pages say so;
• a few of XED’s facts are corrected where the vendors’ manuals say otherwise: some forms move to the ISA set whose CPUID bit they need (the MMX-register forms that SSE added), ISA sets get the CPUID bits that XED lacks (x87 and most of AMD’s extensions), and XED’s AMD chips lose VMX and SMX, with a note on the pages that list them.

XED is Copyright Intel Corporation and licensed under the Apache License 2.0, whose terms apply to the tables derived from it; the text of the pages is our own and licensed under CC BY 4.0.

The intrinsics on the instruction pages and the A–Z index come from the x86 headers of Clang 23.1.2 (commit 85ac56026243). Each one is compiled with that Clang and the machine code is decoded with XED, and an intrinsic is listed only where that confirms a single instruction, and the instruction its doc comment names, if any. The index explains the method. The headers are part of the LLVM Project and licensed under the Apache License 2.0 with LLVM Exceptions; the lists of intrinsics and their signatures are derived from them. Intel’s Intrinsics Guide is not used. Nothing is copied from Intel’s instruction set manuals, whose terms do not allow it: every sentence is written in our own words. Instead, where the manuals describe an instruction, its page links to the page of the manual where the description starts.

Reusing the data#

The complete dataset (features, levels, microarchitectures, exceptions, requirements and sources) can be downloaded as x86.json.

The instruction dataset#

The instruction reference can be downloaded as insn.json (4.9 MB), one JSON object with these members:

• extensions: each extension’s id, name, group, summary, ISA sets and mnemonics, and the URL of its page;
• mnemonics: each mnemonic’s id, name, summary, other spellings, extensions and XED instruction classes; its forms, with syntax, XED iform, encodings in the notation of the reference, encoding space, ISA set and tags, and what XED records about each form (below); and the Clang intrinsics that compile to it, with their signature and, for each form, the iform and the Clang options it needs;
• isa_sets: for each XED ISA set, the CPUID bits it needs, as a list of alternatives whose bits must all be set, and the processors that have it, which chips names: XED’s chips (source is xed) and AMD’s processors after Zen 2 from the CPU data (cpu-data);
• leaves: the leaf functions of GETSEC, ENCLS and ENCLU, with the instruction, register and number that select each, and its CPUID bit;
• groups, sources, license, notice, schema and updated: the groups of extensions, the XED and LLVM releases the data comes from, the terms it comes under, the attribution notices a copy must carry, the version of the format, 1, which changes when a member changes its meaning or goes away, and the date of the newest page;
• name, url and documentation: the name of the dataset, the page of the reference and this description.

What XED records about a form is in these members of the form:

• operands: the operands of the syntax in order, each as its name and what the form does with it, ["r8", "rcw"]; {k} is the opmask of the operand before it;
• implicit: the operands that the syntax leaves out, such as AL for CMPXCHG, RFLAGS or the stack, also as name and action, with "NF=0" added when an APX form uses the operand only with that setting;
• flags: the flags the form tests or writes, as a list of cases, each with flags, which maps each flag to a code, and when, where the case applies only to a shift count, an APX NF setting or, on a page of several conditions such as CMOVcc, one of them; may marks a case that writes the flags only in some cases, as a shift by CL does;
• exceptions: the exception class, the set of exception conditions that XED gives the form, such as SSE_TYPE_2, or null;
• attributes: the attributes of XED that the pages show, such as LOCKABLE or MXCSR; RING0 marks the forms that need CPL 0;
• tuple, only on forms with embedded broadcast: XED’s tuple type of the memory operand, FULL, HALF or QUARTER.

The actions are XED’s: r read, w written, rw both, rcw read and conditionally written, cw conditionally written, cr conditionally read, and crw conditionally read and always written; push, pop and pop2 push or pop the x87 register stack, and addr is an operand of which only the address is used, as in LEA. The flag codes are T tested, M modified, 0 cleared, 1 set, U undefined, P loaded from the stack and A loaded from AH; TM is tested, then modified.

The summaries, like the rest of the site, are under CC BY 4.0. The forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chips are derived from Intel XED and come under its Apache License 2.0, and the intrinsics, derived from Clang’s headers, under the Apache License 2.0 with LLVM Exceptions. The file carries their notices, and so does insn-NOTICE.txt next to it.

The text and data of this site are licensed under CC BY 4.0: you may copy and adapt them, including commercially, as long as you credit x86-64.net with a link. Code, such as the x86-64-level script, is licensed under the MIT license. The fonts are Inter and Fira Mono, under the SIL Open Font License.

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