AMD (low power)
Puma
AMD Puma (2014) supports x86-64-v2.
- x86-64 level
- x86-64-v2
- Vendor
- AMD
- First products
- 2014
- Products
- A-series and E-series APUs (Beema, Mullins)
- Segments
- GCC target
-march=btver2- Optimization
- Optimizing code for Jaguar and Puma
AMD calls the core Puma+. Like Jaguar it is AMD Family 16h, all of which GCC treats as -march=btver2.
Product lines
| Product line | Segment | Socket | Source |
|---|---|---|---|
| A-Series and E-Series (Beema) | mobile | FT3b (BGA) | ir.amd.com |
| A-Series Micro and E-Series Micro (Mullins) | mobile | FT3b (BGA) | ir.amd.com |
| A-Series and E-Series (Carrizo-L) | mobile | FP4 (BGA) | ir.amd.com |
| G-Series (Steppe Eagle, Crowned Eagle) | embedded | FT3b (BGA) | ir.amd.com |
Why not x86-64-v3?
Puma lacks AVX2, BMI2 and FMA, all of which x86-64-v3 requires.
Feature checklist
| Feature | Puma | Enumerated by | Linux flag |
|---|---|---|---|
| x86-64-v1 | |||
| CMOV | Yes | CPUID.01H:EDX[15] | cmov |
| CX8 | Yes | CPUID.01H:EDX[8] | cx8 |
| FPU | Yes | CPUID.01H:EDX[0] | fpu |
| FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| MMX | Yes | CPUID.01H:EDX[23] | mmx |
| OSFXSR via FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| SCE | Yes | CPUID.80000001H:EDX[11] | syscall |
| SSE | Yes | CPUID.01H:EDX[25] | sse |
| SSE2 | Yes | CPUID.01H:EDX[26] | sse2 |
| x86-64-v2 | |||
| CMPXCHG16B | Yes | CPUID.01H:ECX[13] | cx16 |
| LAHF-SAHF | Yes | CPUID.80000001H:ECX[0] | lahf_lm |
| POPCNT | Yes | CPUID.01H:ECX[23] | popcnt |
| SSE3 | Yes | CPUID.01H:ECX[0] | pni |
| SSE4.1 | Yes | CPUID.01H:ECX[19] | sse4_1 |
| SSE4.2 | Yes | CPUID.01H:ECX[20] | sse4_2 |
| SSSE3 | Yes | CPUID.01H:ECX[9] | ssse3 |
| x86-64-v3 | |||
| AVX | Yes | CPUID.01H:ECX[28] | avx |
| AVX2 | No | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 |
| BMI1 | Yes | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 |
| BMI2 | No | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 |
| F16C | Yes | CPUID.01H:ECX[29] | f16c |
| FMA | No | CPUID.01H:ECX[12] | fma |
| LZCNT | Yes | CPUID.80000001H:ECX[5] | abm |
| MOVBE | Yes | CPUID.01H:ECX[22] | movbe |
| OSXSAVE via XSAVE | Yes | CPUID.01H:ECX[26] | xsave |
| x86-64-v4 | |||
| AVX512F | No | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f |
| AVX512BW | No | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw |
| AVX512CD | No | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd |
| AVX512DQ | No | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq |
| AVX512VL | No | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl |
Other extensions
Notable extensions outside the x86-64 levels. Vendors sometimes disable these on individual models. Linked names lead to the extension's instructions.
Known vulnerabilities
The CVEs that the sources of the vulnerability list name as affecting Puma, in all of its models or in some of them.
- CVE-2022-29900 Retbleed: Retbleed (AMD)
- CVE-2018-3639 Speculative Store Bypass
- CVE-2017-5753 Spectre variant 1: Bounds Check Bypass
- CVE-2017-5715 Spectre variant 2: Branch Target Injection
Other AMD (low power) microarchitectures
Sources
- GCC -march=btver2 (processor alias table)
- Next-Generation Mobile APUs Extend AMD Performance Leadership, Add Cutting-Edge Features and Enhanced Security (AMD press release, April 29, 2014): The Beema and Mullins APUs, with up to four “Puma+” cores.
- Linux 7.3 Documentation/hwmon/k10temp.rst: AMD Family 16h, Kabini and Mullins
- GCC common/config/i386/cpuinfo.h: AMD Family 16h is btver2