Intel Core (client)
Arrow Lake
Intel Arrow Lake (2024) supports x86-64-v3.
- x86-64 level
- x86-64-v3
- Vendor
- Intel
- First products
- 2024
- Products
- Core Ultra 200S, 200HX, 200H and 200U
- Segments
- Cores
- Lion Cove P-cores and Skymont E-cores (Core Ultra 200S, 200HX and 200H, with Crestmont E-cores on the 200H's SoC tile); Redwood Cove P-cores and Crestmont E-cores (200U)
- GCC target
-march=arrowlake-s- Optimization
- Optimizing code for Lion Cove
Intel's map of performance events gives the Core Ultra 200U (model B5H) Meteor Lake's Redwood Cove and Crestmont event lists, not Arrow Lake's, and Linux's performance-monitoring driver sets that model up as it does Meteor Lake. GCC's table of processor models selects -march=arrowlake-s for Arrow Lake S (model C6H) but -march=arrowlake for Arrow Lake H and U (models C5H and B5H), which leaves out AVX-VNNI-INT16, SHA512, SM3 and SM4; Intel's extensions reference introduces these with Arrow Lake S.
Product lines
Why not x86-64-v4?
Arrow Lake lacks AVX512BW, AVX512CD, AVX512DQ, AVX512F and AVX512VL, all of which x86-64-v4 requires.
Feature checklist
| Feature | Arrow Lake | Enumerated by | Linux flag |
|---|---|---|---|
| x86-64-v1 | |||
| CMOV | Yes | CPUID.01H:EDX[15] | cmov |
| CX8 | Yes | CPUID.01H:EDX[8] | cx8 |
| FPU | Yes | CPUID.01H:EDX[0] | fpu |
| FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| MMX | Yes | CPUID.01H:EDX[23] | mmx |
| OSFXSR via FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| SCE | Yes | CPUID.80000001H:EDX[11] | syscall |
| SSE | Yes | CPUID.01H:EDX[25] | sse |
| SSE2 | Yes | CPUID.01H:EDX[26] | sse2 |
| x86-64-v2 | |||
| CMPXCHG16B | Yes | CPUID.01H:ECX[13] | cx16 |
| LAHF-SAHF | Yes | CPUID.80000001H:ECX[0] | lahf_lm |
| POPCNT | Yes | CPUID.01H:ECX[23] | popcnt |
| SSE3 | Yes | CPUID.01H:ECX[0] | pni |
| SSE4.1 | Yes | CPUID.01H:ECX[19] | sse4_1 |
| SSE4.2 | Yes | CPUID.01H:ECX[20] | sse4_2 |
| SSSE3 | Yes | CPUID.01H:ECX[9] | ssse3 |
| x86-64-v3 | |||
| AVX | Yes | CPUID.01H:ECX[28] | avx |
| AVX2 | Yes | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 |
| BMI1 | Yes | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 |
| BMI2 | Yes | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 |
| F16C | Yes | CPUID.01H:ECX[29] | f16c |
| FMA | Yes | CPUID.01H:ECX[12] | fma |
| LZCNT | Yes | CPUID.80000001H:ECX[5] | abm |
| MOVBE | Yes | CPUID.01H:ECX[22] | movbe |
| OSXSAVE via XSAVE | Yes | CPUID.01H:ECX[26] | xsave |
| x86-64-v4 | |||
| AVX512F | No | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f |
| AVX512BW | No | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw |
| AVX512CD | No | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd |
| AVX512DQ | No | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq |
| AVX512VL | No | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl |
Other extensions
Notable extensions outside the x86-64 levels. Vendors sometimes disable these on individual models. Linked names lead to the extension's instructions.
- AES-NI
- PCLMULQDQ
- SHA
- RDRAND
- RDSEED
- ADX
- CLWB
- WAITPKG
- MOVDIRI
- MOVDIR64B
- GFNI
- VAES
- VPCLMULQDQ
- AVX-VNNI
- AVX-IFMA
- AVX-VNNI-INT8
- AVX-NE-CONVERT
Known vulnerabilities
The CVEs that the sources of the vulnerability list name as affecting Arrow Lake, in all of its models or in some of them.
- CVE-2026-20760 Intel processor errata: Overlapping protected memory ranges
- CVE-2025-40300 VMSCAPE
- CVE-2025-35973 Intel processor errata: Ring 0 value handling
- CVE-2025-31648 Intel processor errata: Microcode flow value handling
- CVE-2025-24495 Branch Prediction Unit Initialization
- CVE-2025-20109 Stream Cache Isolation: Stream cache isolation (2025)
- CVE-2025-20054 Intel processor errata: Core management exception
- CVE-2025-20012 Intel processor errata: Incorrect behavior order: Core Ultra
- CVE-2024-45332 Branch Privilege Injection: Indirect Branch Predictor Delayed Updates
- CVE-2022-28693 Retbleed: Restricted RSB Alternate behavior
- CVE-2022-26373 Spectre variant 2: Post-barrier Return Stack Buffer Predictions Some models
- CVE-2022-0002 Spectre variant 2: Intra-mode Branch Target Injection
- CVE-2022-0001 Spectre variant 2: Branch History Injection
- CVE-2021-0089 Speculative Code Store Bypass
- CVE-2021-0086 Floating Point Value Injection
- CVE-2019-1125 Spectre variant 1: Spectre v1 swapgs
- CVE-2018-3639 Speculative Store Bypass
- CVE-2017-5753 Spectre variant 1: Bounds Check Bypass
- CVE-2017-5715 Spectre variant 2: Branch Target Injection
Other Intel Core (client) microarchitectures
- NetBurst (Prescott, Nocona) 2004 v1
- Core (Merom, Conroe) 2006 v1
- Penryn 2007 v1
- Nehalem 2008 v2
- Westmere 2010 v2
- Sandy Bridge 2011 v2
- Ivy Bridge 2012 v2
- Haswell 2013 v3
- Broadwell 2014 v3
- Skylake 2015 v3
- Kaby Lake 2016 v3
- Coffee Lake 2017 v3
- Cannon Lake 2018 v4
- Comet Lake 2019 v3
- Ice Lake (client) 2019 v4
- Tiger Lake 2020 v4
- Alder Lake 2021 v3
- Rocket Lake 2021 v4
- Raptor Lake 2022 v3
- Meteor Lake 2023 v3
- Arrow Lake 2024 v3
- Lunar Lake 2024 v3
- Panther Lake 2026 v3
- Nova Lake announced v4
Sources
- GCC -march=arrowlake-s feature set (PTA_ARROWLAKE_S)
- GCC -march=arrowlake feature set (PTA_ARROWLAKE)
- GCC gcc/common/config/i386/cpuinfo.h: models B5H and C5H select -march=arrowlake, C6H -march=arrowlake-s
- Intel Architecture Instruction Set Extensions and Future Features Programming Reference, 319433-062, Tables 1-1 and 1-2: Gives models C6H, C5H and B5H as Arrow Lake S, H and U, and lists Arrow Lake S, not H, as the first with AVX-VNNI-INT16, SHA512, SM3 and SM4 (VEX).
- Intel perfmon mapfile.csv: the event lists of models 06_B5H, 06_C5H and 06_C6H: Model B5: the Redwood Cove (Core) and Crestmont (Atom) lists of Meteor Lake. Model C5: Lion Cove (Core), Skymont (Atom) and Crestmont (LowPower_Atom). Model C6: Lion Cove (Core) and Skymont (Atom).
- Intel Core Ultra 200H and 200U Series Processors Datasheet, Volume 1 of 2, 842704-002, Table 1: Both lines have two E-cores on the SoC tile besides those on the compute tile; the 200U has 2 P-cores and 8 compute-tile E-cores.
- Linux 7.3 arch/x86/include/asm/intel-family.h: INTEL_ARROWLAKE_H (Lion Cove / Skymont), INTEL_ARROWLAKE, INTEL_ARROWLAKE_U: Names cores only on the Arrow Lake H line.
- Linux 7.3 arch/x86/events/intel/core.c: INTEL_ARROWLAKE_U in the Meteor Lake case
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 335592-093, Table 2-1: Models 06_C6H, 06_C5H and 06_B5H: Core Ultra (Series 2) processors, Arrow Lake S, H and U.
- Intel ARK: Products formerly Arrow Lake: Launch dates; the earliest is Q4'24 (Core Ultra 9 285K).