Intel Core (client)
Ice Lake (client)
Intel Ice Lake (client) (2019) supports x86-64-v4.
- x86-64 level
- x86-64-v4
- Vendor
- Intel
- First products
- 2019
- Products
- 10th generation Core mobile processors (Ice Lake)
- Segments
- GCC target
-march=icelake-client- Optimization
- Optimizing code for Ice Lake to Rocket Lake
Intel's optimization manual counts CLWB among the instructions that Ice Lake client adds, and says support may vary by product. GCC's -march=icelake-client, LLVM's icelake-client and XED's Ice Lake chip leave it out, as does the SDM's table of when each extension first appeared, so the CLWB page does not list this processor.
Product lines
Feature checklist
| Feature | Ice Lake (client) | Enumerated by | Linux flag |
|---|---|---|---|
| x86-64-v1 | |||
| CMOV | Yes | CPUID.01H:EDX[15] | cmov |
| CX8 | Yes | CPUID.01H:EDX[8] | cx8 |
| FPU | Yes | CPUID.01H:EDX[0] | fpu |
| FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| MMX | Yes | CPUID.01H:EDX[23] | mmx |
| OSFXSR via FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| SCE | Yes | CPUID.80000001H:EDX[11] | syscall |
| SSE | Yes | CPUID.01H:EDX[25] | sse |
| SSE2 | Yes | CPUID.01H:EDX[26] | sse2 |
| x86-64-v2 | |||
| CMPXCHG16B | Yes | CPUID.01H:ECX[13] | cx16 |
| LAHF-SAHF | Yes | CPUID.80000001H:ECX[0] | lahf_lm |
| POPCNT | Yes | CPUID.01H:ECX[23] | popcnt |
| SSE3 | Yes | CPUID.01H:ECX[0] | pni |
| SSE4.1 | Yes | CPUID.01H:ECX[19] | sse4_1 |
| SSE4.2 | Yes | CPUID.01H:ECX[20] | sse4_2 |
| SSSE3 | Yes | CPUID.01H:ECX[9] | ssse3 |
| x86-64-v3 | |||
| AVX | Yes | CPUID.01H:ECX[28] | avx |
| AVX2 | Yes | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 |
| BMI1 | Yes | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 |
| BMI2 | Yes | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 |
| F16C | Yes | CPUID.01H:ECX[29] | f16c |
| FMA | Yes | CPUID.01H:ECX[12] | fma |
| LZCNT | Yes | CPUID.80000001H:ECX[5] | abm |
| MOVBE | Yes | CPUID.01H:ECX[22] | movbe |
| OSXSAVE via XSAVE | Yes | CPUID.01H:ECX[26] | xsave |
| x86-64-v4 | |||
| AVX512F | Yes | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f |
| AVX512BW | Yes | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw |
| AVX512CD | Yes | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd |
| AVX512DQ | Yes | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq |
| AVX512VL | Yes | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl |
Other extensions
Notable extensions outside the x86-64 levels. Vendors sometimes disable these on individual models. Linked names lead to the extension's instructions.
- AES-NI
- PCLMULQDQ
- SHA
- RDRAND
- RDSEED
- ADX
- GFNI
- VAES
- VPCLMULQDQ
- AVX512-IFMA
- AVX512-VBMI
- AVX512-VBMI2
- AVX512-VNNI
- AVX512-BITALG
- AVX512-VPOPCNTDQ
Known vulnerabilities
The CVEs that the sources of the vulnerability list name as affecting Ice Lake (client), in all of its models or in some of them.
- CVE-2026-20917 Load Value Injection: Load Value Injection: zero data
- CVE-2025-31648 Intel processor errata: Microcode flow value handling
- CVE-2025-20623 Branch Privilege Injection: Shared predictor state: 10th generation Core
- CVE-2024-45332 Branch Privilege Injection: Indirect Branch Predictor Delayed Updates
- CVE-2024-28956 Indirect Target Selection Some models
- CVE-2024-24968 Intel processor errata: Hardware logic state machines Some models
- CVE-2024-24853 Intel BIOS, UEFI and SMM: SMI Transfer Monitor transition order
- CVE-2023-23583 Redundant Prefix Issue
- CVE-2022-40982 Gather Data Sampling
- CVE-2022-38090 Intel SGX: Stale data read from the legacy xAPIC under SGX
- CVE-2022-28693 Retbleed: Restricted RSB Alternate behavior
- CVE-2022-26373 Spectre variant 2: Post-barrier Return Stack Buffer Predictions
- CVE-2022-21233 Stale Data Read from Legacy xAPIC
- CVE-2022-21166 Processor MMIO Stale Data: Device Register Partial Write
- CVE-2022-21151 Optimization Removal of Security-critical Code
- CVE-2022-21125 Processor MMIO Stale Data: Shared Buffers Data Sampling
- CVE-2022-21123 Processor MMIO Stale Data: Shared Buffers Data Read
- CVE-2022-0004 Intel BIOS, UEFI and SMM: Boot Guard and TXT lock override
- CVE-2022-0002 Spectre variant 2: Intra-mode Branch Target Injection
- CVE-2022-0001 Spectre variant 2: Branch History Injection
- CVE-2021-0145 Fast Store Forwarding Predictor: Fast Store Forwarding Predictor: cross-domain
- CVE-2021-0089 Speculative Code Store Bypass
- CVE-2021-0086 Floating Point Value Injection
- CVE-2020-24512 Influence of Trivial Data Value in Cache Policy
- CVE-2020-24511 Spectre variant 2: IBRS Guest/Host
- CVE-2020-8698 Fast Store Forwarding Predictor: Fast Store Forwarding Predictor: cross-thread
- CVE-2020-8695 RAPL Energy Reporting: RAPL energy reporting
- CVE-2020-0551 Load Value Injection Some models
- CVE-2019-1125 Spectre variant 1: Spectre v1 swapgs
- CVE-2018-12207 iTLB multihit: Machine Check Error Avoidance on Page Size Change
- CVE-2018-12126 Microarchitectural Data Sampling: Microarchitectural Store Buffer Data Sampling
- CVE-2018-3639 Speculative Store Bypass
- CVE-2017-5753 Spectre variant 1: Bounds Check Bypass
- CVE-2017-5715 Spectre variant 2: Branch Target Injection
Other Intel Core (client) microarchitectures
- NetBurst (Prescott, Nocona) 2004 v1
- Core (Merom, Conroe) 2006 v1
- Penryn 2007 v1
- Nehalem 2008 v2
- Westmere 2010 v2
- Sandy Bridge 2011 v2
- Ivy Bridge 2012 v2
- Haswell 2013 v3
- Broadwell 2014 v3
- Skylake 2015 v3
- Kaby Lake 2016 v3
- Coffee Lake 2017 v3
- Cannon Lake 2018 v4
- Comet Lake 2019 v3
- Ice Lake (client) 2019 v4
- Tiger Lake 2020 v4
- Alder Lake 2021 v3
- Rocket Lake 2021 v4
- Raptor Lake 2022 v3
- Meteor Lake 2023 v3
- Arrow Lake 2024 v3
- Lunar Lake 2024 v3
- Panther Lake 2026 v3
- Nova Lake announced v4
Sources
- GCC -march=icelake-client feature set (PTA_ICELAKE_CLIENT)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 335592-093, Table 2-1: Model 06_7EH: 10th generation Core processors, Ice Lake.
- Intel ARK: Products formerly Ice Lake: Launch dates; the earliest is Q3'19 (Core i7-1065G7).
- Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1, 248966-051, Sections 2.5 and 2.5.1.5: Lists CLWB among the new instructions of Ice Lake client, with support that may depend on the product.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, 253665-093, Table 5-2: The CLWB row names Xeon Scalable, Tremont and Tiger Lake processors, not Ice Lake client.
- LLVM llvm/lib/Target/X86/X86.td: the icelake-client features, without CLWB, which icelake-server adds