Intel Atom and E-cores
Silvermont
Intel Silvermont (2013) supports x86-64-v2.
- x86-64 level
- x86-64-v2
- Vendor
- Intel
- First products
- 2013
- Products
- Atom Z3000 (Bay Trail) and C2000; Celeron and Pentium J1000/N2000
- Segments
- GCC target
-march=silvermont- Optimization
- Optimizing code for Silvermont to Goldmont Plus
Intel's manuals count AES-NI among Silvermont's instruction sets, and Intel's product pages list it for the Atom Z3740, E3845 and C2750 but not for the Celeron J1900 and N2930. GCC's -march=silvermont and LLVM's silvermont leave it out and add it from Goldmont, and this entry follows them; XED's Silvermont chip has it, so the AES-NI pages list this processor.
Product lines
| Product line | Segment | Socket | Source |
|---|---|---|---|
| Atom Z3000 (Bay Trail) | mobile | BGA1380, BGA592 | intel.com |
| Atom E3800 (Bay Trail) | embedded | BGA1170 | intel.com |
| Pentium and Celeron J1000/J2000 (Bay Trail) | desktop | BGA1170 | intel.com |
| Pentium and Celeron N2000/N3000 (Bay Trail) | mobile | BGA1170 | intel.com |
| Atom Z3400 (Merrifield) | mobile | FC-MB5796 (BGA) | intel.com |
| Atom Z3500 (Moorefield) | mobile | FC-MB5T1064 (BGA) | intel.com |
| Atom C2000 (Avoton) | server | BGA1283 | intel.com |
| Atom C2000 (Rangeley) | embedded | BGA1283 | intel.com |
Why not x86-64-v3?
Silvermont lacks AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT and XSAVE, all of which x86-64-v3 requires.
Feature checklist
| Feature | Silvermont | Enumerated by | Linux flag |
|---|---|---|---|
| x86-64-v1 | |||
| CMOV | Yes | CPUID.01H:EDX[15] | cmov |
| CX8 | Yes | CPUID.01H:EDX[8] | cx8 |
| FPU | Yes | CPUID.01H:EDX[0] | fpu |
| FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| MMX | Yes | CPUID.01H:EDX[23] | mmx |
| OSFXSR via FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| SCE | Yes | CPUID.80000001H:EDX[11] | syscall |
| SSE | Yes | CPUID.01H:EDX[25] | sse |
| SSE2 | Yes | CPUID.01H:EDX[26] | sse2 |
| x86-64-v2 | |||
| CMPXCHG16B | Yes | CPUID.01H:ECX[13] | cx16 |
| LAHF-SAHF | Yes | CPUID.80000001H:ECX[0] | lahf_lm |
| POPCNT | Yes | CPUID.01H:ECX[23] | popcnt |
| SSE3 | Yes | CPUID.01H:ECX[0] | pni |
| SSE4.1 | Yes | CPUID.01H:ECX[19] | sse4_1 |
| SSE4.2 | Yes | CPUID.01H:ECX[20] | sse4_2 |
| SSSE3 | Yes | CPUID.01H:ECX[9] | ssse3 |
| x86-64-v3 | |||
| AVX | No | CPUID.01H:ECX[28] | avx |
| AVX2 | No | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 |
| BMI1 | No | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 |
| BMI2 | No | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 |
| F16C | No | CPUID.01H:ECX[29] | f16c |
| FMA | No | CPUID.01H:ECX[12] | fma |
| LZCNT | No | CPUID.80000001H:ECX[5] | abm |
| MOVBE | Yes | CPUID.01H:ECX[22] | movbe |
| OSXSAVE via XSAVE | No | CPUID.01H:ECX[26] | xsave |
| x86-64-v4 | |||
| AVX512F | No | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f |
| AVX512BW | No | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw |
| AVX512CD | No | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd |
| AVX512DQ | No | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq |
| AVX512VL | No | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl |
Other extensions
Notable extensions outside the x86-64 levels. Vendors sometimes disable these on individual models. Linked names lead to the extension's instructions.
Known vulnerabilities
The CVEs that the sources of the vulnerability list name as affecting Silvermont, in all of its models or in some of them.
- CVE-2018-12126 Microarchitectural Data Sampling: Microarchitectural Store Buffer Data Sampling
- CVE-2017-5754 Meltdown: Rogue Data Cache Load
- CVE-2017-5753 Spectre variant 1: Bounds Check Bypass
- CVE-2017-5715 Spectre variant 2: Branch Target Injection
Other Intel Atom and E-cores microarchitectures
Sources
- GCC -march=silvermont feature set (PTA_SILVERMONT)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, 253665-093, Section 2.1.15: The Atom C2000, E3000 and S1000 series are based on Silvermont (2013), whose processors support AES-NI and PCLMULQDQ besides SSE4.2.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, 253665-093, Table 5-2: The AES-NI and PCLMULQDQ row names the Atom processors based on Silvermont.
- Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 2, 356477-051, Sections 6.5 and 6.8.2.13: Lists AES-NI and PCLMULQDQ among Silvermont’s instruction set enhancements.
- LLVM llvm/lib/Target/X86/X86.td: the silvermont features, without AES, which the goldmont features add
- Intel ARK: Intel Atom Processor Z3740: Intel AES New Instructions: Yes.
- Intel ARK: Intel Atom Processor E3845: Intel AES New Instructions: Yes.
- Intel ARK: Intel Atom Processor C2750: Intel AES New Instructions: Yes.
- Intel ARK: Intel Celeron Processor J1900: Intel AES New Instructions: No.
- Intel ARK: Intel Celeron Processor N2930: Intel AES New Instructions: No.
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 335592-093, Table 2-1: Models 06_37H, 06_4AH, 06_4DH, 06_5AH and 06_5DH: Atom E3000, Z3400, Z3500, Z3600, Z3700, C2000 and x3-C3000 series.
- Intel ARK: Products formerly Bay Trail: Launch dates; the earliest is Q3'13 (Atom Z3740).
- Linux 7.3 arch/x86/include/asm/intel-family.h: INTEL_ATOM_SILVERMONT (Bay Trail), _D (Avoton, Rangeley), _MID (Merrifield), _MID2 (Anniedale)