Intel Atom and E-cores
Tremont
Intel Tremont (2020) supports x86-64-v2.
- x86-64 level
- x86-64-v2
- Vendor
- Intel
- First products
- 2020
- Products
- Pentium Silver and Celeron N4500/N5100/N6000 (Jasper Lake); Atom x6000E (Elkhart Lake); Lakefield
- Segments
- GCC target
-march=tremont- Optimization
- Optimizing code for Tremont
LLVM's Tremont (TRM) feature list gives it only CLWB and GFNI; it defers MOVDIRI, MOVDIR64B and WAITPKG to Alder Lake (ADL) and CLDEMOTE further to Sierra Forest (SRF), though the final feature sets of Alder Lake and Sierra Forest end up the same either way. GCC's -march=tremont and the SDM's Table 5-2 both give Tremont all five directly, and this entry follows GCC, as it already does for GFNI.
Product lines
| Product line | Segment | Socket | Source |
|---|---|---|---|
| Pentium Silver and Celeron (Jasper Lake) | mobile | BGA1338 | intel.com |
| Atom x6000E (Elkhart Lake) | embedded | BGA1493 | intel.com |
| Pentium and Celeron J6000/N6000 (Elkhart Lake) | embedded | BGA1493 | intel.com |
| Atom P5000 (Snow Ridge) | server | BGA2106 | intel.com |
| Atom C5000 (Parker Ridge) | server | BGA2106 | intel.com |
| Core with Intel Hybrid Technology (Lakefield) | mobile | FC-CSP1016 (BGA) | intel.com |
Why not x86-64-v3?
Tremont lacks AVX, AVX2, BMI1, BMI2, F16C, FMA and LZCNT, all of which x86-64-v3 requires.
Feature checklist
| Feature | Tremont | Enumerated by | Linux flag |
|---|---|---|---|
| x86-64-v1 | |||
| CMOV | Yes | CPUID.01H:EDX[15] | cmov |
| CX8 | Yes | CPUID.01H:EDX[8] | cx8 |
| FPU | Yes | CPUID.01H:EDX[0] | fpu |
| FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| MMX | Yes | CPUID.01H:EDX[23] | mmx |
| OSFXSR via FXSR | Yes | CPUID.01H:EDX[24] | fxsr |
| SCE | Yes | CPUID.80000001H:EDX[11] | syscall |
| SSE | Yes | CPUID.01H:EDX[25] | sse |
| SSE2 | Yes | CPUID.01H:EDX[26] | sse2 |
| x86-64-v2 | |||
| CMPXCHG16B | Yes | CPUID.01H:ECX[13] | cx16 |
| LAHF-SAHF | Yes | CPUID.80000001H:ECX[0] | lahf_lm |
| POPCNT | Yes | CPUID.01H:ECX[23] | popcnt |
| SSE3 | Yes | CPUID.01H:ECX[0] | pni |
| SSE4.1 | Yes | CPUID.01H:ECX[19] | sse4_1 |
| SSE4.2 | Yes | CPUID.01H:ECX[20] | sse4_2 |
| SSSE3 | Yes | CPUID.01H:ECX[9] | ssse3 |
| x86-64-v3 | |||
| AVX | No | CPUID.01H:ECX[28] | avx |
| AVX2 | No | CPUID.(EAX=07H,ECX=0):EBX[5] | avx2 |
| BMI1 | No | CPUID.(EAX=07H,ECX=0):EBX[3] | bmi1 |
| BMI2 | No | CPUID.(EAX=07H,ECX=0):EBX[8] | bmi2 |
| F16C | No | CPUID.01H:ECX[29] | f16c |
| FMA | No | CPUID.01H:ECX[12] | fma |
| LZCNT | No | CPUID.80000001H:ECX[5] | abm |
| MOVBE | Yes | CPUID.01H:ECX[22] | movbe |
| OSXSAVE via XSAVE | Yes | CPUID.01H:ECX[26] | xsave |
| x86-64-v4 | |||
| AVX512F | No | CPUID.(EAX=07H,ECX=0):EBX[16] | avx512f |
| AVX512BW | No | CPUID.(EAX=07H,ECX=0):EBX[30] | avx512bw |
| AVX512CD | No | CPUID.(EAX=07H,ECX=0):EBX[28] | avx512cd |
| AVX512DQ | No | CPUID.(EAX=07H,ECX=0):EBX[17] | avx512dq |
| AVX512VL | No | CPUID.(EAX=07H,ECX=0):EBX[31] | avx512vl |
Other extensions
Notable extensions outside the x86-64 levels. Vendors sometimes disable these on individual models. Linked names lead to the extension's instructions.
Known vulnerabilities
The CVEs that the sources of the vulnerability list name as affecting Tremont, in all of its models or in some of them.
- CVE-2023-28746 Register File Data Sampling
- CVE-2022-38090 Intel SGX: Stale data read from the legacy xAPIC under SGX
- CVE-2022-21233 Stale Data Read from Legacy xAPIC
- CVE-2022-21166 Processor MMIO Stale Data: Device Register Partial Write
- CVE-2022-0004 Intel BIOS, UEFI and SMM: Boot Guard and TXT lock override
- CVE-2022-0002 Spectre variant 2: Intra-mode Branch Target Injection
- CVE-2022-0001 Spectre variant 2: Branch History Injection
- CVE-2021-33120 Missing Page Fault
- CVE-2021-0089 Speculative Code Store Bypass
- CVE-2021-0086 Floating Point Value Injection
- CVE-2020-24513 Atom Processor Domain Bypass Some models
- CVE-2020-8695 RAPL Energy Reporting: RAPL energy reporting Some models
- CVE-2019-1125 Spectre variant 1: Spectre v1 swapgs
- CVE-2018-3639 Speculative Store Bypass
- CVE-2017-5753 Spectre variant 1: Bounds Check Bypass
- CVE-2017-5715 Spectre variant 2: Branch Target Injection
Other Intel Atom and E-cores microarchitectures
Sources
- GCC -march=tremont feature set (PTA_TREMONT)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, 253665-093, Table 5-2: The CLWB, CLDEMOTE, direct-store (MOVDIRI/MOVDIR64B) and user-wait (WAITPKG) rows all name the Tremont-based Atom processor.
- LLVM llvm/lib/Target/X86/X86.td: the Tremont (TRM) feature list, with only CLWB and GFNI
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 4, 335592-093, Table 2-1: Models 06_86H, 06_96H and 06_9CH: Atom, Celeron, Pentium and Pentium Silver processors based on Tremont.
- Intel ARK: Products formerly Snow Ridge: Launch dates; the earliest is Q1'20 (Atom P5942B).
- Linux 7.3 arch/x86/include/asm/intel-family.h: INTEL_ATOM_TREMONT_D (Jacobsville), INTEL_ATOM_TREMONT (Elkhart Lake), INTEL_ATOM_TREMONT_L (Jasper Lake)
- Linux 7.3 arch/x86/include/asm/intel-family.h: INTEL_LAKEFIELD, Sunny Cove / Tremont