Name
Non-coherent Secure Processor memory access
Vulnerability
AMD Secure Processor and SMU firmware
Kind
Firmware
CVE published
2026-06-09 CVE record
Advisories
AMD-SB-3039
Benedict Schlueter and Shweta Shinde of ETH Zurich found that a system setting the hypervisor controls decides whether the AMD Secure Processor’s memory requests stay coherent with the CPU caches. With coherency off, the Secure Processor can read stale data from DRAM while it copies pages and updates their metadata, so writes a guest still holds in the caches are lost, which undermines the integrity of SEV-SNP guests. AMD’s record puts the flaw in the access control of an IOMMU register interface. It affects the fourth and fifth EPYC generations; exploiting it needs a malicious hypervisor and precise timing.

Affected processors

2 of the 2 microarchitectures listed are affected in all or some of their models.

What the sources say of each microarchitecture.
MicroarchitectureStatusDetailSource
Zen 4AffectedEPYC 8004 and 9004, EPYC Embedded 8004 and 9004amd.com
Zen 5AffectedEPYC 9005, EPYC Embedded 9005amd.com

Mitigations

  • Firmware: GenoaPI 1.0.0.H, TurinPI 1.0.0.8, EmbGenoaPI-SP5 1.0.0.D and EmbeddedTurinPI_SP5 1004, from late 2025 and 2026. Source.

Sources

  1. AMD-SB-3039: ASP non-Coherent Memory Access