{"chips":{"ALDER_LAKE":{"name":"Alder Lake","source":"xed","vendor":"intel"},"AMD_BULLDOZER":{"name":"Bulldozer","source":"xed","vendor":"amd"},"AMD_K10":{"name":"K10 (Family 10h)","source":"xed","vendor":"amd"},"AMD_PILEDRIVER":{"name":"Piledriver","source":"xed","vendor":"amd"},"AMD_ZEN":{"name":"Zen","source":"xed","vendor":"amd"},"AMD_ZEN2":{"name":"Zen 2","source":"xed","vendor":"amd"},"AMD_ZENPLUS":{"name":"Zen+","source":"xed","vendor":"amd"},"ARROW_LAKE":{"name":"Arrow Lake","source":"xed","vendor":"intel"},"BONNELL":{"name":"Bonnell","source":"xed","vendor":"intel"},"BROADWELL":{"name":"Broadwell","source":"xed","vendor":"intel"},"CANNONLAKE":{"name":"Cannon Lake","source":"xed","vendor":"intel"},"CASCADE_LAKE":{"name":"Cascade Lake","source":"xed","vendor":"intel"},"CLEARWATER_FOREST":{"name":"Clearwater Forest","source":"xed","vendor":"intel"},"COMET_LAKE":{"name":"Comet Lake","source":"xed","vendor":"intel"},"COOPER_LAKE":{"name":"Cooper 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Conroe)","source":"xed","vendor":"intel"},"NEHALEM":{"name":"Nehalem","source":"xed","vendor":"intel"},"NOVA_LAKE":{"name":"Nova Lake","source":"xed","vendor":"intel"},"P4PRESCOTT":{"name":"NetBurst (Prescott, Nocona)","source":"xed","vendor":"intel"},"PANTHER_LAKE":{"name":"Panther Lake","source":"xed","vendor":"intel"},"PENRYN":{"name":"Penryn","source":"xed","vendor":"intel"},"SALTWELL":{"name":"Saltwell","source":"xed","vendor":"intel"},"SANDYBRIDGE":{"name":"Sandy Bridge","source":"xed","vendor":"intel"},"SAPPHIRE_RAPIDS":{"name":"Sapphire Rapids","source":"xed","vendor":"intel"},"SIERRA_FOREST":{"name":"Sierra Forest","source":"xed","vendor":"intel"},"SILVERMONT":{"name":"Silvermont","source":"xed","vendor":"intel"},"SKYLAKE":{"name":"Skylake","source":"xed","vendor":"intel"},"SKYLAKE_SERVER":{"name":"Skylake-SP","source":"xed","vendor":"intel"},"SNOW_RIDGE":{"name":"Snow Ridge","source":"xed","vendor":"intel"},"TIGER_LAKE":{"name":"Tiger Lake","source":"xed","vendor":"intel"},"TREMONT":{"name":"Tremont","source":"xed","vendor":"intel"},"WESTMERE":{"name":"Westmere","source":"xed","vendor":"intel"},"zen-3":{"name":"Zen 3","source":"cpu-data","vendor":"amd"},"zen-4":{"name":"Zen 4","source":"cpu-data","vendor":"amd"},"zen-5":{"name":"Zen 5","source":"cpu-data","vendor":"amd"},"zen-6":{"name":"Zen 6","source":"cpu-data","vendor":"amd"}},"documentation":"https://x86-64.net/about/#instruction-dataset","extensions":[{"group":"general","id":"general-purpose","isa_sets":["FAT_NOP","I186","I386","I486REAL","I86","LONGMODE","PAUSE","PENTIUMREAL","PPRO","PPRO_UD0_LONG","PPRO_UD0_SHORT","PREFETCH_NOP"],"mnemonics":["aaa","aad","aam","aas","adc","add","and","bound","bsf","bsr","bswap","bt","btc","btr","bts","call","cbw","cdq","cdqe","clc","cld","cli","cmc","cmp","cmps","cmpxchg","cmpxchg8b","cpuid","cqo","cwd","cwde","daa","das","dec","div","enter","idiv","imul","in","inc","ins","int","int1","int3","into","iret","jcc","jcxz","jecxz","jmp","jrcxz","lds","lea","leave","les","lfs","lgs","lods","loop","loope","loopne","lss","mov","movs","movsx","movsxd","movzx","mul","neg","nop","not","or","out","outs","pause","pop","popa","popf","push","pusha","pushf","rcl","rcr","ret","rol","ror","salc","sar","sbb","scas","setcc","shl","shld","shr","shrd","stc","std","sti","stos","sub","test","ud0","ud1","ud2","udb","xadd","xchg","xlat","xor"],"name":"General-purpose","summary":"The integer arithmetic, logic, shift, bit, data-movement, jump and call, string, stack and flag instructions that every x86-64 processor runs, from those of the 8086 to those that 64-bit mode added.","url":"https://x86-64.net/isa/general-purpose/"},{"group":"general","id":"cmov","isa_sets":["CMOV"],"mnemonics":["cmovcc"],"name":"CMOV","summary":"Conditional moves: CMOVcc copies a register or memory operand into a register only if a condition on the flags holds, so that code can choose between two values without a branch.","url":"https://x86-64.net/isa/cmov/"},{"group":"general","id":"lahf-sahf","isa_sets":["LAHF"],"mnemonics":["lahf","sahf"],"name":"LAHF-SAHF","summary":"LAHF and SAHF in 64-bit mode, which the first x86-64 processors lacked there, so a CPUID bit says whether they work; they always work in the other modes.","url":"https://x86-64.net/isa/lahf-sahf/"},{"group":"general","id":"popcnt","isa_sets":["POPCNT"],"mnemonics":["popcnt"],"name":"POPCNT","summary":"POPCNT counts the set bits of a 16-, 32- or 64-bit operand in one instruction.","url":"https://x86-64.net/isa/popcnt/"},{"group":"general","id":"lzcnt","isa_sets":["LZCNT"],"mnemonics":["lzcnt"],"name":"LZCNT","summary":"LZCNT counts the leading zero bits of an operand; unlike BSR it has a defined result for zero, the operand size, and it reports that case in CF.","url":"https://x86-64.net/isa/lzcnt/"},{"group":"general","id":"bmi1","isa_sets":["BMI1"],"mnemonics":["andn","bextr","blsi","blsmsk","blsr","tzcnt"],"name":"BMI1","summary":"The first Bit Manipulation Instructions: ANDN, BEXTR, BLSI, BLSMSK, BLSR and TZCNT, which combine, extract, isolate and count bits in one VEX-encoded instruction each (TZCNT is a legacy encoding).","url":"https://x86-64.net/isa/bmi1/"},{"group":"general","id":"bmi2","isa_sets":["BMI2"],"mnemonics":["bzhi","mulx","pdep","pext","rorx","sarx","shlx","shrx"],"name":"BMI2","summary":"The second Bit Manipulation Instructions: BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX and SHRX, among them shifts and a multiply that leave the flags alone and bit deposit and extract.","url":"https://x86-64.net/isa/bmi2/"},{"group":"general","id":"adx","isa_sets":["ADOX_ADCX"],"mnemonics":["adcx","adox"],"name":"ADX","summary":"ADCX and ADOX add with a carry through CF alone or OF alone, so that two independent carry chains can run interleaved, as in multiplying big numbers.","url":"https://x86-64.net/isa/adx/"},{"group":"general","id":"movbe","isa_sets":["MOVBE"],"mnemonics":["movbe"],"name":"MOVBE","summary":"MOVBE loads or stores a value with its bytes reversed, converting between little- and big-endian data as it moves.","url":"https://x86-64.net/isa/movbe/"},{"group":"general","id":"rdrand","isa_sets":["RDRAND"],"mnemonics":["rdrand"],"name":"RDRAND","summary":"RDRAND returns random numbers from a generator in the processor that its hardware entropy source keeps reseeding.","url":"https://x86-64.net/isa/rdrand/"},{"group":"general","id":"rdseed","isa_sets":["RDSEED"],"mnemonics":["rdseed"],"name":"RDSEED","summary":"RDSEED returns random numbers straight from the processor's hardware entropy source, meant for seeding software generators.","url":"https://x86-64.net/isa/rdseed/"},{"group":"memory","id":"cmpxchg16b","isa_sets":["CMPXCHG16B"],"mnemonics":["cmpxchg16b"],"name":"CMPXCHG16B","summary":"CMPXCHG16B compares and exchanges 16 bytes of memory atomically, for lock-free structures that update a pointer and a counter together.","url":"https://x86-64.net/isa/cmpxchg16b/"},{"group":"memory","id":"clflush","isa_sets":["CLFSH"],"mnemonics":["clflush"],"name":"CLFLUSH","summary":"CLFLUSH writes a cache line back to memory and removes it from every cache in the system.","url":"https://x86-64.net/isa/clflush/"},{"group":"memory","id":"clflushopt","isa_sets":["CLFLUSHOPT"],"mnemonics":["clflushopt"],"name":"CLFLUSHOPT","summary":"CLFLUSHOPT evicts a cache line like CLFLUSH but with weaker ordering, so that the flushes of many lines can overlap.","url":"https://x86-64.net/isa/clflushopt/"},{"group":"memory","id":"clwb","isa_sets":["CLWB"],"mnemonics":["clwb"],"name":"CLWB","summary":"CLWB writes a modified cache line back to memory without necessarily evicting it, which makes stores to persistent memory durable at less cost than a flush.","url":"https://x86-64.net/isa/clwb/"},{"group":"memory","id":"cldemote","isa_sets":["CLDEMOTE"],"mnemonics":["cldemote"],"name":"CLDEMOTE","summary":"CLDEMOTE hints that a cache line should move from the core's own caches to a shared level, so that another core can read it sooner.","url":"https://x86-64.net/isa/cldemote/"},{"group":"system","id":"rdtscp","isa_sets":["RDTSCP"],"mnemonics":["rdtscp"],"name":"RDTSCP","summary":"RDTSCP reads the time-stamp counter together with IA32_TSC_AUX, where operating systems keep the number of the processor, after earlier instructions have executed.","url":"https://x86-64.net/isa/rdtscp/"},{"group":"system","id":"rdpid","isa_sets":["RDPID"],"mnemonics":["rdpid"],"name":"RDPID","summary":"RDPID reads IA32_TSC_AUX, where operating systems keep the number of the processor, without the time stamp that RDTSCP also returns.","url":"https://x86-64.net/isa/rdpid/"},{"group":"system","id":"system","isa_sets":["I286PROTECTED","I286REAL","I486","I486REAL","I86","LONGMODE","PENTIUMREAL","RDPMC"],"mnemonics":["arpl","clts","hlt","invd","invlpg","lar","lgdt","lidt","lldt","lmsw","lsl","ltr","rdmsr","rdpmc","rdtsc","rsm","sgdt","sidt","sldt","smsw","str","swapgs","verr","verw","wbinvd","wrmsr"],"name":"System","summary":"The instructions that operating systems, hypervisors and firmware use to control the processor: descriptor tables, control and model-specific registers, caches and TLBs, and the time-stamp counter.","url":"https://x86-64.net/isa/system/"},{"group":"system","id":"syscall","isa_sets":["AMD","LONGMODE"],"mnemonics":["syscall","sysret"],"name":"SYSCALL/SYSRET","summary":"SYSCALL and SYSRET, the fast system call and return of 64-bit mode, which change privilege level with an entry point and segments held in MSRs instead of a gate in the IDT.","url":"https://x86-64.net/isa/syscall/"},{"group":"system","id":"sysenter","isa_sets":["SEP"],"mnemonics":["sysenter","sysexit"],"name":"SYSENTER/SYSEXIT","summary":"SYSENTER and SYSEXIT, a fast system call and return that take the kernel's entry point and stack from MSRs, which 32-bit code uses on Intel processors.","url":"https://x86-64.net/isa/sysenter/"},{"group":"system","id":"vmx","isa_sets":["VMFUNC","VTX"],"mnemonics":["invept","invvpid","vmcall","vmclear","vmfunc","vmlaunch","vmptrld","vmptrst","vmread","vmresume","vmwrite","vmxoff","vmxon"],"name":"VMX","summary":"VMX, Intel's virtualization extension (VT-x), lets a hypervisor run guests directly on the processor, each virtual processor described by a control structure (VMCS) in memory.","url":"https://x86-64.net/isa/vmx/"},{"group":"system","id":"tdx","isa_sets":["TDX"],"mnemonics":["seamcall","seamops","seamret","tdcall"],"name":"TDX","summary":"Intel TDX runs confidential virtual machines, trust domains, under the Intel TDX module, which the hypervisor and the guests call with the SEAM instructions.","url":"https://x86-64.net/isa/tdx/"},{"group":"system","id":"smx","isa_sets":["SMX"],"mnemonics":["getsec"],"name":"SMX","summary":"SMX, the Safer Mode Extensions behind Intel TXT, adds GETSEC, whose leaf functions launch a measured environment from code that the processor has authenticated.","url":"https://x86-64.net/isa/smx/"},{"group":"system","id":"sgx","isa_sets":["SGX","SGX_ENCLV"],"mnemonics":["encls","enclu","enclv"],"name":"SGX","summary":"Intel SGX protects code and data in enclaves, memory that even the operating system cannot read; ENCLS and ENCLU perform its leaf functions, such as ECREATE and EENTER.","url":"https://x86-64.net/isa/sgx/"},{"group":"system","id":"fxsr","isa_sets":["FXSAVE","FXSAVE64"],"mnemonics":["fxrstor","fxsave"],"name":"FXSR","summary":"FXSAVE and FXRSTOR save and restore the x87, MMX and SSE registers and MXCSR in one 512-byte area; the operating system sets CR4.OSFXSR to say it saves SSE state this way.","url":"https://x86-64.net/isa/fxsr/"},{"group":"system","id":"xsave","isa_sets":["XSAVE"],"mnemonics":["xgetbv","xrstor","xsave","xsetbv"],"name":"XSAVE","summary":"The XSAVE feature set saves and restores processor state in numbered components that bitmaps select, so one mechanism covers x87, SSE, AVX, AVX-512, AMX and the state that later extensions add.","url":"https://x86-64.net/isa/xsave/"},{"group":"system","id":"xsaveopt","isa_sets":["XSAVEOPT"],"mnemonics":["xsaveopt"],"name":"XSAVEOPT","summary":"XSAVEOPT saves like XSAVE but may skip state components that have not changed since the last XRSTOR or are in their initial state, which saves time on context switches.","url":"https://x86-64.net/isa/xsaveopt/"},{"group":"system","id":"xsavec","isa_sets":["XSAVEC"],"mnemonics":["xsavec"],"name":"XSAVEC","summary":"XSAVEC saves processor state in the compacted format, which packs the selected components together and leaves out those in their initial state.","url":"https://x86-64.net/isa/xsavec/"},{"group":"system","id":"xsaves","isa_sets":["XSAVES"],"mnemonics":["xrstors","xsaves"],"name":"XSAVES","summary":"XSAVES and XRSTORS save and restore supervisor state components, such as the Processor Trace and CET registers, together with user state, in the compacted format; ring 0 only.","url":"https://x86-64.net/isa/xsaves/"},{"group":"system","id":"monitor","isa_sets":["MONITOR"],"mnemonics":["monitor","mwait"],"name":"MONITOR/MWAIT","summary":"MONITOR arms address monitoring and MWAIT waits in an optimized state for a store to the monitored range or an interrupt; kernels use them to idle processors.","url":"https://x86-64.net/isa/monitor/"},{"group":"system","id":"waitpkg","isa_sets":["WAITPKG"],"mnemonics":["tpause","umonitor","umwait"],"name":"WAITPKG","summary":"UMONITOR, UMWAIT and TPAUSE let user code wait in a power-saving state for a store to an address or for a time-stamp deadline, instead of spinning.","url":"https://x86-64.net/isa/waitpkg/"},{"group":"system","id":"serialize","isa_sets":["SERIALIZE"],"mnemonics":["serialize"],"name":"SERIALIZE","summary":"SERIALIZE waits until all earlier instructions have completed and their stores have drained, without the register side effects of CPUID or the control transfer of IRET.","url":"https://x86-64.net/isa/serialize/"},{"group":"system","id":"smap","isa_sets":["SMAP"],"mnemonics":["clac","stac"],"name":"SMAP","summary":"Supervisor Mode Access Prevention stops the kernel from reading or writing user pages, unless it sets the AC flag with STAC for the access and clears it again with CLAC.","url":"https://x86-64.net/isa/smap/"},{"group":"system","id":"pku","isa_sets":["PKU"],"mnemonics":["rdpkru","wrpkru"],"name":"PKU","summary":"Protection keys for user pages: each page carries one of 16 keys, and RDPKRU and WRPKRU read and write the per-thread register that disables access or writes for each key.","url":"https://x86-64.net/isa/pku/"},{"group":"system","id":"fsgsbase","isa_sets":["RDWRFSGS"],"mnemonics":["rdfsbase","rdgsbase","wrfsbase","wrgsbase"],"name":"FSGSBASE","summary":"RDFSBASE, RDGSBASE, WRFSBASE and WRGSBASE read and write the FS and GS segment bases in 64-bit mode, once the operating system has enabled them in CR4.","url":"https://x86-64.net/isa/fsgsbase/"},{"group":"system","id":"invpcid","isa_sets":["INVPCID"],"mnemonics":["invpcid"],"name":"INVPCID","summary":"INVPCID invalidates TLB entries by process-context identifier (PCID): of one address, of one context, or of all contexts with or without global pages; ring 0 only.","url":"https://x86-64.net/isa/invpcid/"},{"group":"system","id":"cet","isa_sets":["CET"],"mnemonics":["clrssbsy","endbr32","endbr64","incsspd","incsspq","rdsspd","rdsspq","rstorssp","saveprevssp","setssbsy","wrssd","wrssq","wrussd","wrussq"],"name":"CET","summary":"Control-flow Enforcement Technology: shadow stacks, which hold a copy of every return address that ordinary stores cannot change, and indirect branch tracking, which allows indirect jumps only to ENDBR instructions.","url":"https://x86-64.net/isa/cet/"},{"group":"system","id":"uintr","isa_sets":["UINTR"],"mnemonics":["clui","senduipi","stui","testui","uiret"],"name":"UINTR","summary":"User interrupts: a thread can send an interrupt with SENDUIPI to a thread on another core, whose handler then runs in user mode without the kernel.","url":"https://x86-64.net/isa/uintr/"},{"group":"system","id":"mpx","isa_sets":["MPX"],"mnemonics":["bndcl","bndcn","bndcu","bndldx","bndmk","bndmov","bndstx"],"name":"MPX","summary":"Memory Protection Extensions added bound registers and instructions that check pointers against bounds; Intel has deprecated MPX, and its core processors since Ice Lake lack it.","url":"https://x86-64.net/isa/mpx/"},{"group":"system","id":"pconfig","isa_sets":["PCONFIG"],"mnemonics":["pconfig"],"name":"PCONFIG","summary":"PCONFIG configures platform features through leaf functions selected by EAX, such as programming the keys of multi-key total memory encryption; ring 0 only.","url":"https://x86-64.net/isa/pconfig/"},{"group":"system","id":"wbnoinvd","isa_sets":["WBNOINVD"],"mnemonics":["wbnoinvd"],"name":"WBNOINVD","summary":"WBNOINVD writes every modified cache line back to memory, as WBINVD does, but leaves the lines valid in the caches.","url":"https://x86-64.net/isa/wbnoinvd/"},{"group":"system","id":"ptwrite","isa_sets":["PTWRITE"],"mnemonics":["ptwrite"],"name":"PTWRITE","summary":"PTWRITE lets software put a value of its own into the Intel Processor Trace stream, for example to mark events in a trace.","url":"https://x86-64.net/isa/ptwrite/"},{"group":"system","id":"enqcmd","isa_sets":["ENQCMD"],"mnemonics":["enqcmd","enqcmds"],"name":"ENQCMD","summary":"ENQCMD and ENQCMDS send a 64-byte command to the shared work queue of a device as one atomic write, tagged with a process address space ID, and learn from ZF whether the device took it.","url":"https://x86-64.net/isa/enqcmd/"},{"group":"memory","id":"movdiri","isa_sets":["MOVDIRI"],"mnemonics":["movdiri"],"name":"MOVDIRI","summary":"MOVDIRI writes a doubleword or quadword to memory with a direct store that bypasses the caches, for writing to device registers.","url":"https://x86-64.net/isa/movdiri/"},{"group":"memory","id":"movdir64b","isa_sets":["MOVDIR64B"],"mnemonics":["movdir64b"],"name":"MOVDIR64B","summary":"MOVDIR64B copies 64 bytes from memory to a 64-byte aligned address as one direct store, the way to hand a work descriptor to a device.","url":"https://x86-64.net/isa/movdir64b/"},{"group":"memory","id":"rtm","isa_sets":["RTM"],"mnemonics":["xabort","xbegin","xend","xtest"],"name":"RTM","summary":"Restricted Transactional Memory: XBEGIN starts a transaction whose memory updates all become visible on XEND, or are all rolled back on a conflict or an abort.","url":"https://x86-64.net/isa/rtm/"},{"group":"memory","id":"tsxldtrk","isa_sets":["TSX_LDTRK"],"mnemonics":["xresldtrk","xsusldtrk"],"name":"TSXLDTRK","summary":"Suspend load address tracking: within an RTM transaction, XSUSLDTRK and XRESLDTRK bracket loads that stay out of the read set, so they cannot cause conflicts.","url":"https://x86-64.net/isa/tsxldtrk/"},{"group":"crypto","id":"keylocker","isa_sets":["KEYLOCKER","KEYLOCKER_WIDE"],"mnemonics":["aesdec128kl","aesdec256kl","aesdecwide128kl","aesdecwide256kl","aesenc128kl","aesenc256kl","aesencwide128kl","aesencwide256kl","encodekey128","encodekey256","loadiwkey"],"name":"Key Locker","summary":"Key Locker turns AES keys into handles that only the processor can unwrap, so that software encrypts and decrypts without keeping the keys in memory.","url":"https://x86-64.net/isa/keylocker/"},{"group":"general","id":"apx-f","isa_sets":["APX_F","APX_F_ADX","APX_F_ADX_N3","APX_F_AMX","APX_F_AMX_BASE","APX_F_AMX_MOVRS","APX_F_BMI1","APX_F_BMI1_N3","APX_F_BMI2","APX_F_BMI2_N3","APX_F_CET","APX_F_CMPCCXADD","APX_F_ENQCMD","APX_F_INVPCID","APX_F_KOPB","APX_F_KOPD","APX_F_KOPQ","APX_F_KOPW","APX_F_LZCNT","APX_F_LZCNT_N3","APX_F_MOVBE","APX_F_MOVDIR64B","APX_F_MOVDIRI","APX_F_MOVRS","APX_F_MSR_IMM","APX_F_N3","APX_F_POPCNT","APX_F_POPCNT_N3","APX_F_RAO_INT","APX_F_USER_MSR","APX_F_VMX"],"mnemonics":["aadd","aand","adc","adcx","add","adox","and","andn","aor","axor","bextr","blsi","blsmsk","blsr","bzhi","ccmpscc","cfcmovcc","cmovcc","cmpccxadd","crc32","ctestscc","dec","div","enqcmd","enqcmds","idiv","imul","inc","invept","invpcid","invvpid","jmpabs","kmovb","kmovd","kmovq","kmovw","ldtilecfg","lzcnt","movbe","movdir64b","movdiri","movrs","mul","mulx","neg","not","or","pdep","pext","pop2","pop2p","popcnt","popp","push2","push2p","pushp","rcl","rcr","rdmsr","rol","ror","rorx","sar","sarx","sbb","setcc","shl","shld","shlx","shr","shrd","shrx","sttilecfg","sub","tileloadd","tileloaddrs","tileloaddrst1","tileloaddt1","tilestored","tzcnt","urdmsr","uwrmsr","wrmsrns","wrssd","wrssq","wrussd","wrussq","xor"],"name":"APX","summary":"Intel's Advanced Performance Extensions double the general-purpose registers to 32 and give integer instructions a separate destination, optional flag suppression, conditional compares and paired pushes and pops, in 64-bit mode.","url":"https://x86-64.net/isa/apx-f/"},{"group":"x87-mmx","id":"x87","isa_sets":["FCMOV","FCOMI","X87"],"mnemonics":["f2xm1","fabs","fadd","faddp","fbld","fbstp","fchs","fcmovb","fcmovbe","fcmove","fcmovnb","fcmovnbe","fcmovne","fcmovnu","fcmovu","fcom","fcomi","fcomip","fcomp","fcompp","fcos","fdecstp","fdiv","fdivp","fdivr","fdivrp","ffree","ffreep","fiadd","ficom","ficomp","fidiv","fidivr","fild","fimul","fincstp","fist","fistp","fisub","fisubr","fld","fld1","fldcw","fldenv","fldl2e","fldl2t","fldlg2","fldln2","fldpi","fldz","fmul","fmulp","fnclex","fndisi","fneni","fninit","fnop","fnsave","fnsetpm","fnstcw","fnstenv","fnstsw","fpatan","fprem","fprem1","fptan","frndint","frstor","fscale","fsin","fsincos","fsqrt","fst","fstp","fsub","fsubp","fsubr","fsubrp","ftst","fucom","fucomi","fucomip","fucomp","fucompp","fwait","fxam","fxch","fxtract","fyl2x","fyl2xp1"],"name":"x87","summary":"The x87 floating-point unit computes in 80-bit extended precision on a stack of eight registers; x86-64 code still uses it for long double.","url":"https://x86-64.net/isa/x87/"},{"group":"x87-mmx","id":"mmx","isa_sets":["PENTIUMMMX"],"mnemonics":["emms","movd","movq","packssdw","packsswb","packuswb","paddb","paddd","paddsb","paddsw","paddusb","paddusw","paddw","pand","pandn","pcmpeqb","pcmpeqd","pcmpeqw","pcmpgtb","pcmpgtd","pcmpgtw","pmaddwd","pmulhw","pmullw","por","pslld","psllq","psllw","psrad","psraw","psrld","psrlq","psrlw","psubb","psubd","psubsb","psubsw","psubusb","psubusw","psubw","punpckhbw","punpckhdq","punpckhwd","punpcklbw","punpckldq","punpcklwd","pxor"],"name":"MMX","summary":"MMX, the first SIMD extension of x86, works on packed bytes, words and doublewords in eight 64-bit registers that share the x87 registers.","url":"https://x86-64.net/isa/mmx/"},{"group":"vector","id":"sse","isa_sets":["SSE","SSEMXCSR","SSE_PREFETCH"],"mnemonics":["addps","addss","andnps","andps","cmpps","cmpss","comiss","cvtpi2ps","cvtps2pi","cvtsi2ss","cvtss2si","cvttps2pi","cvttss2si","divps","divss","ldmxcsr","maskmovq","maxps","maxss","minps","minss","movaps","movhlps","movhps","movlhps","movlps","movmskps","movntps","movntq","movss","movups","mulps","mulss","orps","pavgb","pavgw","pextrw","pinsrw","pmaxsw","pmaxub","pminsw","pminub","pmovmskb","pmulhuw","prefetchnta","prefetcht0","prefetcht1","prefetcht2","psadbw","pshufw","rcpps","rcpss","rsqrtps","rsqrtss","sfence","shufps","sqrtps","sqrtss","stmxcsr","subps","subss","ucomiss","unpckhps","unpcklps","xorps"],"name":"SSE","summary":"SSE, the Streaming SIMD Extensions of the Pentium III: eight 128-bit XMM registers (16 in 64-bit mode), four-wide single-precision arithmetic, MXCSR and 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extends the XMM registers to double precision and to integer vectors of every width, and adds LFENCE, MFENCE and MOVNTI; x86-64 code does its float and double arithmetic with it.","url":"https://x86-64.net/isa/sse2/"},{"group":"vector","id":"sse3","isa_sets":["SSE3","SSE3X87"],"mnemonics":["addsubpd","addsubps","fisttp","haddpd","haddps","hsubpd","hsubps","lddqu","movddup","movshdup","movsldup"],"name":"SSE3","summary":"SSE3 adds horizontal additions and subtractions, the ADDSUB instructions for complex arithmetic, duplicating moves, LDDQU and the truncating x87 store FISTTP.","url":"https://x86-64.net/isa/sse3/"},{"group":"vector","id":"ssse3","isa_sets":["SSSE3","SSSE3MMX"],"mnemonics":["pabsb","pabsd","pabsw","palignr","phaddd","phaddsw","phaddw","phsubd","phsubsw","phsubw","pmaddubsw","pmulhrsw","pshufb","psignb","psignd","psignw"],"name":"SSSE3","summary":"Supplemental SSE3 adds byte shuffles with PSHUFB, byte alignment with PALIGNR, horizontal integer additions, absolute values, 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widens the vector registers to 256 bits (YMM) and adds the VEX encoding, whose instructions take a separate destination and have no alignment requirement; it brings floating-point arithmetic to 256 bits.","url":"https://x86-64.net/isa/avx/"},{"group":"vector","id":"avx2","isa_sets":["AVX2","AVX2GATHER"],"mnemonics":["vbroadcasti128","vbroadcastsd","vbroadcastss","vextracti128","vgatherdpd","vgatherdps","vgatherqpd","vgatherqps","vinserti128","vmovntdqa","vmpsadbw","vpabsb","vpabsd","vpabsw","vpackssdw","vpacksswb","vpackusdw","vpackuswb","vpaddb","vpaddd","vpaddq","vpaddsb","vpaddsw","vpaddusb","vpaddusw","vpaddw","vpalignr","vpand","vpandn","vpavgb","vpavgw","vpblendd","vpblendvb","vpblendw","vpbroadcastb","vpbroadcastd","vpbroadcastq","vpbroadcastw","vpcmpeqb","vpcmpeqd","vpcmpeqq","vpcmpeqw","vpcmpgtb","vpcmpgtd","vpcmpgtq","vpcmpgtw","vperm2i128","vpermd","vpermpd","vpermps","vpermq","vpgatherdd","vpgatherdq","vpgatherqd","vpgatherqq","vphaddd","vphaddsw","vphaddw","vphsubd","vphsubsw","vphsubw","vpmaddubsw","vpmaddwd","vpmaskmovd","vpmaskmovq","vpmaxsb","vpmaxsd","vpmaxsw","vpmaxub","vpmaxud","vpmaxuw","vpminsb","vpminsd","vpminsw","vpminub","vpminud","vpminuw","vpmovmskb","vpmovsxbd","vpmovsxbq","vpmovsxbw","vpmovsxdq","vpmovsxwd","vpmovsxwq","vpmovzxbd","vpmovzxbq","vpmovzxbw","vpmovzxdq","vpmovzxwd","vpmovzxwq","vpmuldq","vpmulhrsw","vpmulhuw","vpmulhw","vpmulld","vpmullw","vpmuludq","vpor","vpsadbw","vpshufb","vpshufd","vpshufhw","vpshuflw","vpsignb","vpsignd","vpsignw","vpslld","vpslldq","vpsllq","vpsllvd","vpsllvq","vpsllw","vpsrad","vpsravd","vpsraw","vpsrld","vpsrldq","vpsrlq","vpsrlvd","vpsrlvq","vpsrlw","vpsubb","vpsubd","vpsubq","vpsubsb","vpsubsw","vpsubusb","vpsubusw","vpsubw","vpunpckhbw","vpunpckhdq","vpunpckhqdq","vpunpckhwd","vpunpcklbw","vpunpckldq","vpunpcklqdq","vpunpcklwd","vpxor"],"name":"AVX2","summary":"AVX2 brings integer vector instructions to 256 bits and adds gathers, permutes across 128-bit lanes, shifts by a count per element, broadcasts and masked moves.","url":"https://x86-64.net/isa/avx2/"},{"group":"vector","id":"f16c","isa_sets":["F16C"],"mnemonics":["vcvtph2ps","vcvtps2ph"],"name":"F16C","summary":"F16C converts packed half-precision values to single precision and back, for data stored in the compact 16-bit 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first version of the converged AVX10 vector ISA: the AVX-512 instruction set of Sapphire Rapids, enumerated by one feature bit and a version number instead of a feature bit per subset.","url":"https://x86-64.net/isa/avx10-1/"},{"group":"vector","id":"avx10-2","isa_sets":["AVX10_2_BF16_128","AVX10_2_BF16_256","AVX10_2_BF16_512","AVX10_2_BF16_SCALAR","AVX512_COM_EF_SCALAR","AVX512_FP16_CONVERT_128","AVX512_FP16_CONVERT_256","AVX512_FP16_CONVERT_512","AVX512_FP8_CONVERT_128","AVX512_FP8_CONVERT_256","AVX512_FP8_CONVERT_512","AVX512_MEDIAX_128","AVX512_MEDIAX_256","AVX512_MEDIAX_512","AVX512_MINMAX_128","AVX512_MINMAX_256","AVX512_MINMAX_512","AVX512_MINMAX_SCALAR","AVX512_MOVZXC_128","AVX512_SAT_CVT_128","AVX512_SAT_CVT_256","AVX512_SAT_CVT_512","AVX512_SAT_CVT_DS_128","AVX512_SAT_CVT_DS_256","AVX512_SAT_CVT_DS_512","AVX512_SAT_CVT_DS_SCALAR","AVX512_VNNI_FP16_128","AVX512_VNNI_FP16_256","AVX512_VNNI_FP16_512","AVX512_VNNI_INT16_128","AVX512_VNNI_INT16_256","AVX512_VNNI_INT16_512","AVX512_VNNI_INT8_128","AVX512_VNNI_INT8_256","AVX512_VNNI_INT8_512"],"mnemonics":["vaddbf16","vcmpbf16","vcomisbf16","vcomxsd","vcomxsh","vcomxss","vcvt2ph2bf8","vcvt2ph2bf8s","vcvt2ph2hf8","vcvt2ph2hf8s","vcvt2ps2phx","vcvtbf162ibs","vcvtbf162iubs","vcvtbiasph2bf8","vcvtbiasph2bf8s","vcvtbiasph2hf8","vcvtbiasph2hf8s","vcvthf82ph","vcvtph2bf8","vcvtph2bf8s","vcvtph2hf8","vcvtph2hf8s","vcvtph2ibs","vcvtph2iubs","vcvtps2ibs","vcvtps2iubs","vcvttbf162ibs","vcvttbf162iubs","vcvttpd2dqs","vcvttpd2qqs","vcvttpd2udqs","vcvttpd2uqqs","vcvttph2ibs","vcvttph2iubs","vcvttps2dqs","vcvttps2ibs","vcvttps2iubs","vcvttps2qqs","vcvttps2udqs","vcvttps2uqqs","vcvttsd2sis","vcvttsd2usis","vcvttss2sis","vcvttss2usis","vdivbf16","vdpphps","vfmadd132bf16","vfmadd213bf16","vfmadd231bf16","vfmsub132bf16","vfmsub213bf16","vfmsub231bf16","vfnmadd132bf16","vfnmadd213bf16","vfnmadd231bf16","vfnmsub132bf16","vfnmsub213bf16","vfnmsub231bf16","vfpclassbf16","vgetexpbf16","vgetmantbf16","vmaxbf16","vminbf16","vminmaxbf16","vminmaxpd","vminmaxph","vminmaxps","vminmaxsd","vminmaxsh","vminmaxss","vmovd","vmovw","vmpsadbw","vmulbf16","vpdpbssd","vpdpbssds","vpdpbsud","vpdpbsuds","vpdpbuud","vpdpbuuds","vpdpwsud","vpdpwsuds","vpdpwusd","vpdpwusds","vpdpwuud","vpdpwuuds","vrcpbf16","vreducebf16","vrndscalebf16","vrsqrtbf16","vscalefbf16","vsqrtbf16","vsubbf16","vucomxsd","vucomxsh","vucomxss"],"name":"AVX10.2","summary":"AVX10 version 2 adds to AVX10.1 bfloat16 arithmetic, FP8 conversions, saturating float-to-integer conversions, IEEE 754-2019 minimum and maximum, more dot products and scalar compares that set the flags for every relation; it is the first version Intel plans for both client and server processors.","url":"https://x86-64.net/isa/avx10-2/"},{"group":"vector","id":"avx10-v2-aux","isa_sets":["AVX10_V2_AUX_128","AVX10_V2_AUX_256","AVX10_V2_AUX_512"],"mnemonics":["vcvtbf42hf8","vcvtbf62hf8","vcvtbf82bf4s","vcvtbf82bf6s","vcvtbf82ps","vcvtbiasps2bf8","vcvtbiasps2bf8s","vcvtbiasps2hf8","vcvtbiasps2hf8s","vcvthf62hf8","vcvthf82bf4s","vcvthf82hf6s","vcvthf82ps","vcvtps2bf8","vcvtps2bf8s","vcvtps2hf8","vcvtps2hf8s","vcvtrops2hf8","vcvtrops2hf8s","vpmovssdb","vunpackb"],"name":"AVX10_V2_AUX","summary":"Conversions from single precision to FP8 and between FP8 and the 6- and 4-bit formats of the OCP microscaling specification, defined with ACE.","url":"https://x86-64.net/isa/avx10-v2-aux/"},{"group":"vector","id":"avx512er","isa_sets":["AVX512ER_512","AVX512ER_SCALAR"],"mnemonics":["vexp2pd","vexp2ps","vrcp28pd","vrcp28ps","vrcp28sd","vrcp28ss","vrsqrt28pd","vrsqrt28ps","vrsqrt28sd","vrsqrt28ss"],"name":"AVX512ER","summary":"AVX512ER, the exponential and reciprocal instructions of the Xeon Phi processors, approximates 2^x, 1/x and 1/sqrt(x) in ZMM registers to within 2^-23 or 2^-28.","url":"https://x86-64.net/isa/avx512er/"},{"group":"vector","id":"avx512pf","isa_sets":["AVX512PF_512"],"mnemonics":["vgatherpf0dpd","vgatherpf0dps","vgatherpf0qpd","vgatherpf0qps","vgatherpf1dpd","vgatherpf1dps","vgatherpf1qpd","vgatherpf1qps","vscatterpf0dpd","vscatterpf0dps","vscatterpf0qpd","vscatterpf0qps","vscatterpf1dpd","vscatterpf1dps","vscatterpf1qpd","vscatterpf1qps"],"name":"AVX512PF","summary":"AVX512PF, the gather and scatter prefetches of the Xeon Phi processors, brings the elements that a vector of indices addresses into the first- or second-level cache ahead of a gather or scatter.","url":"https://x86-64.net/isa/avx512pf/"},{"group":"vector","id":"avx512-4fmaps","isa_sets":["AVX512_4FMAPS_512","AVX512_4FMAPS_SCALAR"],"mnemonics":["v4fmaddps","v4fmaddss","v4fnmaddps","v4fnmaddss"],"name":"AVX512_4FMAPS","summary":"AVX512_4FMAPS performs four fused multiply-adds of single-precision values in a row in one instruction, with four consecutive ZMM registers and four values from memory.","url":"https://x86-64.net/isa/avx512-4fmaps/"},{"group":"vector","id":"avx512-4vnniw","isa_sets":["AVX512_4VNNIW_512"],"mnemonics":["vp4dpwssd","vp4dpwssds"],"name":"AVX512_4VNNIW","summary":"AVX512_4VNNIW adds four dot products of signed words to doublewords in one instruction, with four consecutive ZMM registers and memory.","url":"https://x86-64.net/isa/avx512-4vnniw/"},{"group":"vector","id":"avx512-vp2intersect","isa_sets":["AVX512_VP2INTERSECT_128","AVX512_VP2INTERSECT_256","AVX512_VP2INTERSECT_512"],"mnemonics":["vp2intersectd","vp2intersectq"],"name":"AVX512-VP2INTERSECT","summary":"AVX512-VP2INTERSECT finds the elements that two vectors of doublewords or quadwords have in common and writes the answer as a pair of masks.","url":"https://x86-64.net/isa/avx512-vp2intersect/"},{"group":"vector","id":"avx-vnni","isa_sets":["AVX_VNNI"],"mnemonics":["vpdpbusd","vpdpbusds","vpdpwssd","vpdpwssds"],"name":"AVX-VNNI","summary":"VEX-encoded forms of the AVX512-VNNI byte and word dot products, for processors and code without AVX-512.","url":"https://x86-64.net/isa/avx-vnni/"},{"group":"vector","id":"avx-vnni-int8","isa_sets":["AVX_VNNI_INT8"],"mnemonics":["vpdpbssd","vpdpbssds","vpdpbsud","vpdpbsuds","vpdpbuud","vpdpbuuds"],"name":"AVX-VNNI-INT8","summary":"VEX-encoded dot products of 8-bit integers in every combination of signed and unsigned inputs, accumulated into 32-bit integers.","url":"https://x86-64.net/isa/avx-vnni-int8/"},{"group":"vector","id":"avx-vnni-int16","isa_sets":["AVX_VNNI_INT16"],"mnemonics":["vpdpwsud","vpdpwsuds","vpdpwusd","vpdpwusds","vpdpwuud","vpdpwuuds"],"name":"AVX-VNNI-INT16","summary":"VEX-encoded dot products of 16-bit integers with unsigned or mixed signed and unsigned inputs, accumulated into 32-bit integers.","url":"https://x86-64.net/isa/avx-vnni-int16/"},{"group":"vector","id":"avx-ifma","isa_sets":["AVX_IFMA"],"mnemonics":["vpmadd52huq","vpmadd52luq"],"name":"AVX-IFMA","summary":"VEX-encoded multiply-add of 52-bit unsigned integers into 64-bit accumulators, a building block for big-number arithmetic.","url":"https://x86-64.net/isa/avx-ifma/"},{"group":"vector","id":"avx-ne-convert","isa_sets":["AVX_NE_CONVERT"],"mnemonics":["vbcstnebf162ps","vbcstnesh2ps","vcvtneebf162ps","vcvtneeph2ps","vcvtneobf162ps","vcvtneoph2ps","vcvtneps2bf16"],"name":"AVX-NE-CONVERT","summary":"VEX-encoded conversions of bfloat16 and half-precision values to single precision and of single precision to bfloat16, which neither consult MXCSR nor raise floating-point exceptions.","url":"https://x86-64.net/isa/avx-ne-convert/"},{"group":"matrix","id":"amx-tile","isa_sets":["AMX_TILE","AMX_TILE_BASE"],"mnemonics":["ldtilecfg","sttilecfg","tileloadd","tileloaddt1","tilerelease","tilestored","tilezero"],"name":"AMX-TILE","summary":"The base of Advanced Matrix Extensions: eight tile registers of up to 1 KiB each, their configuration, and tile loads and stores.","url":"https://x86-64.net/isa/amx-tile/"},{"group":"matrix","id":"amx-int8","isa_sets":["AMX_INT8"],"mnemonics":["tdpbssd","tdpbsud","tdpbusd","tdpbuud"],"name":"AMX-INT8","summary":"Tile matrix multiplication of 8-bit integers, signed or unsigned, accumulated into 32-bit integers.","url":"https://x86-64.net/isa/amx-int8/"},{"group":"matrix","id":"amx-bf16","isa_sets":["AMX_BF16"],"mnemonics":["tdpbf16ps"],"name":"AMX-BF16","summary":"Tile matrix multiplication of bfloat16 values accumulated into single precision.","url":"https://x86-64.net/isa/amx-bf16/"},{"group":"matrix","id":"amx-fp16","isa_sets":["AMX_FP16"],"mnemonics":["tdpfp16ps"],"name":"AMX-FP16","summary":"Tile matrix multiplication of IEEE half-precision values accumulated into single precision.","url":"https://x86-64.net/isa/amx-fp16/"},{"group":"matrix","id":"amx-complex","isa_sets":["AMX_COMPLEX"],"mnemonics":["tcmmimfp16ps","tcmmrlfp16ps"],"name":"AMX-COMPLEX","summary":"Tile multiplication of complex numbers stored as half-precision pairs, producing the real or the imaginary part in single precision.","url":"https://x86-64.net/isa/amx-complex/"},{"group":"matrix","id":"amx-fp8","isa_sets":["AMX_FP8"],"mnemonics":["tdpbf8ps","tdpbhf8ps","tdphbf8ps","tdphf8ps"],"name":"AMX-FP8","summary":"Tile matrix multiplication of 8-bit floating-point values in the E5M2 and E4M3 formats, accumulated into single precision.","url":"https://x86-64.net/isa/amx-fp8/"},{"group":"matrix","id":"amx-movrs","isa_sets":["AMX_MOVRS"],"mnemonics":["tileloaddrs","tileloaddrst1"],"name":"AMX-MOVRS","summary":"Tile loads with a read-shared hint, for data that many cores read.","url":"https://x86-64.net/isa/amx-movrs/"},{"group":"matrix","id":"amx-avx512","isa_sets":["AMX_AVX512"],"mnemonics":["tcvtrowd2ps","tcvtrowps2bf16h","tcvtrowps2bf16l","tcvtrowps2phh","tcvtrowps2phl","tilemovrow"],"name":"AMX-AVX512","summary":"Moves rows of a tile into ZMM registers, optionally converting them to single precision, bfloat16 or half precision on the way.","url":"https://x86-64.net/isa/amx-avx512/"},{"group":"matrix","id":"ace","isa_sets":["ACE_1","AMX_AVX512","AMX_TILE_BASE"],"mnemonics":["bsrinit","bsrmovf","bsrmovh","bsrmovl","ldtilecfg","sttilecfg","tcvtrowd2ps","tcvtrowps2bf16h","tcvtrowps2bf16l","tcvtrowps2phh","tcvtrowps2phl","tilemovcol","tilemovrow","tilerelease","tilezero","top2bf16ps","top4bssd","top4bsud","top4busd","top4buud","top4mxbf8ps","top4mxbhf8ps","top4mxbssps","top4mxhbf8ps","top4mxhf8ps"],"name":"ACE","summary":"The AI Compute Extensions of the x86 Ecosystem Advisory Group: outer products of data in AVX10 vector registers accumulated into AMX tile registers, with block scale registers for microscaling formats.","url":"https://x86-64.net/isa/ace/"},{"group":"crypto","id":"aes","isa_sets":["AES","AVXAES"],"mnemonics":["aesdec","aesdeclast","aesenc","aesenclast","aesimc","aeskeygenassist","vaesdec","vaesdeclast","vaesenc","vaesenclast","vaesimc","vaeskeygenassist"],"name":"AES-NI","summary":"AES-NI performs whole rounds of AES encryption and decryption on a 128-bit block in one instruction each, and helps with key expansion.","url":"https://x86-64.net/isa/aes/"},{"group":"crypto","id":"pclmulqdq","isa_sets":["PCLMULQDQ"],"mnemonics":["pclmulqdq"],"name":"PCLMULQDQ","summary":"PCLMULQDQ multiplies two 64-bit polynomials over GF(2), without carries, into a 128-bit product.","url":"https://x86-64.net/isa/pclmulqdq/"},{"group":"crypto","id":"sha","isa_sets":["SHA"],"mnemonics":["sha1msg1","sha1msg2","sha1nexte","sha1rnds4","sha256msg1","sha256msg2","sha256rnds2"],"name":"SHA","summary":"The SHA extensions compute rounds and message schedules of SHA-1 and SHA-256 on XMM registers.","url":"https://x86-64.net/isa/sha/"},{"group":"crypto","id":"gfni","isa_sets":["AVX_GFNI","GFNI"],"mnemonics":["gf2p8affineinvqb","gf2p8affineqb","gf2p8mulb","vgf2p8affineinvqb","vgf2p8affineqb","vgf2p8mulb"],"name":"GFNI","summary":"Galois field instructions: byte multiplication in GF(2^8) and affine transformations of bytes by an 8x8 bit matrix, in legacy and VEX forms.","url":"https://x86-64.net/isa/gfni/"},{"group":"crypto","id":"vaes","isa_sets":["VAES"],"mnemonics":["vaesdec","vaesdeclast","vaesenc","vaesenclast"],"name":"VAES","summary":"VAES extends the AES round instructions to 256-bit YMM registers, one block per 128-bit lane; with AVX-512 or AVX10 they reach 512 bits.","url":"https://x86-64.net/isa/vaes/"},{"group":"crypto","id":"vpclmulqdq","isa_sets":["VPCLMULQDQ"],"mnemonics":["vpclmulqdq"],"name":"VPCLMULQDQ","summary":"VPCLMULQDQ performs one carry-less multiplication per 128-bit lane of a YMM register, and of a ZMM register with AVX-512 or AVX10.","url":"https://x86-64.net/isa/vpclmulqdq/"},{"group":"crypto","id":"sha512","isa_sets":["SHA512"],"mnemonics":["vsha512msg1","vsha512msg2","vsha512rnds2"],"name":"SHA512","summary":"VEX-encoded message schedule and round instructions for SHA-384 and SHA-512.","url":"https://x86-64.net/isa/sha512/"},{"group":"crypto","id":"sm3","isa_sets":["SM3"],"mnemonics":["vsm3msg1","vsm3msg2","vsm3rnds2"],"name":"SM3","summary":"VEX-encoded message expansion and round instructions for the SM3 hash function.","url":"https://x86-64.net/isa/sm3/"},{"group":"crypto","id":"sm4","isa_sets":["SM4","SM4_128","SM4_256","SM4_512"],"mnemonics":["vsm4key4","vsm4rnds4"],"name":"SM4","summary":"Key expansion and encryption rounds of the SM4 block cipher, VEX-encoded and, on processors with AVX10, EVEX-encoded up to 512 bits.","url":"https://x86-64.net/isa/sm4/"},{"group":"memory","id":"cmpccxadd","isa_sets":["CMPCCXADD"],"mnemonics":["cmpccxadd"],"name":"CMPccXADD","summary":"Atomic compare and add: compares a value in memory with a register and, if the condition holds, adds another register to memory, returning the old value either way.","url":"https://x86-64.net/isa/cmpccxadd/"},{"group":"memory","id":"rao-int","isa_sets":["RAO_INT"],"mnemonics":["aadd","aand","aor","axor"],"name":"RAO-INT","summary":"Remote atomic operations: atomic add, and, or and xor on memory that return nothing, so the processor may perform them away from the core.","url":"https://x86-64.net/isa/rao-int/"},{"group":"memory","id":"movrs","isa_sets":["AVX10_MOVRS_128","AVX10_MOVRS_256","AVX10_MOVRS_512","MOVRS"],"mnemonics":["movrs","prefetchrst2","vmovrsb","vmovrsd","vmovrsq","vmovrsw"],"name":"MOVRS","summary":"Loads and a prefetch with a read-shared hint, for data that many cores read but rarely write.","url":"https://x86-64.net/isa/movrs/"},{"group":"memory","id":"prefetchi","isa_sets":["ICACHE_PREFETCH"],"mnemonics":["prefetchit0","prefetchit1"],"name":"PREFETCHI","summary":"Prefetches code rather than data, from a RIP-relative address, into the cache hierarchy.","url":"https://x86-64.net/isa/prefetchi/"},{"group":"memory","id":"prefetchwt1","isa_sets":["PREFETCHWT1"],"mnemonics":["prefetchwt1"],"name":"PREFETCHWT1","summary":"PREFETCHWT1 prefetches a cache line into the second-level cache in the exclusive state, ready for the processor to write it.","url":"https://x86-64.net/isa/prefetchwt1/"},{"group":"system","id":"msrlist","isa_sets":["MSRLIST"],"mnemonics":["rdmsrlist","wrmsrlist"],"name":"MSRLIST","summary":"Reads or writes a list of up to 64 model-specific registers with one instruction.","url":"https://x86-64.net/isa/msrlist/"},{"group":"system","id":"wrmsrns","isa_sets":["WRMSRNS"],"mnemonics":["wrmsrns"],"name":"WRMSRNS","summary":"A model-specific register write that, unlike WRMSR, is not serializing.","url":"https://x86-64.net/isa/wrmsrns/"},{"group":"system","id":"msr-imm","isa_sets":["MSR_IMM"],"mnemonics":["rdmsr","wrmsrns"],"name":"MSR_IMM","summary":"Forms of RDMSR and WRMSRNS that take the register number as an immediate and the value in any general-purpose register.","url":"https://x86-64.net/isa/msr-imm/"},{"group":"system","id":"user-msr","isa_sets":["USER_MSR"],"mnemonics":["urdmsr","uwrmsr"],"name":"USER_MSR","summary":"Lets user-mode code read and write the model-specific registers that the operating system allows in a bitmap.","url":"https://x86-64.net/isa/user-msr/"},{"group":"system","id":"fred","isa_sets":["FRED"],"mnemonics":["erets","eretu"],"name":"FRED","summary":"Flexible Return and Event Delivery replaces the IDT-based delivery of interrupts, exceptions and system calls with one mechanism, and adds ERETS and ERETU to return from it.","url":"https://x86-64.net/isa/fred/"},{"group":"system","id":"lkgs","isa_sets":["LKGS"],"mnemonics":["lkgs"],"name":"LKGS","summary":"Loads the GS segment from a selector but writes the descriptor's base address to the IA32_KERNEL_GS_BASE MSR, so a FRED kernel can change a thread's GS without losing its own GS base.","url":"https://x86-64.net/isa/lkgs/"},{"group":"system","id":"hreset","isa_sets":["HRESET"],"mnemonics":["hreset"],"name":"HRESET","summary":"Lets the kernel reset selected history that the processor keeps for its hardware prediction features, as enumerated in CPUID leaf 20H.","url":"https://x86-64.net/isa/hreset/"},{"group":"system","id":"pbndkb","isa_sets":["PBNDKB"],"mnemonics":["pbndkb"],"name":"PBNDKB","summary":"Encrypts and authenticates data with a key tied to the platform, for configuring Total Storage Encryption through PCONFIG.","url":"https://x86-64.net/isa/pbndkb/"},{"group":"system","id":"ibhf","isa_sets":["IBHF"],"mnemonics":["ibhf"],"name":"IBHF","summary":"Indirect Branch History Fence: in ring 0 with BHI_DIS_S set, keeps branch history from before the fence from steering the predicted targets of later indirect branches.","url":"https://x86-64.net/isa/ibhf/"},{"group":"x87-mmx","id":"3dnow","isa_sets":["3DNOW","3DNOW_EXT"],"mnemonics":["femms","pavgusb","pf2id","pf2iw","pfacc","pfadd","pfcmpeq","pfcmpge","pfcmpgt","pfmax","pfmin","pfmul","pfnacc","pfpnacc","pfrcp","pfrcpit1","pfrcpit2","pfrsqit1","pfrsqrt","pfsub","pfsubr","pi2fd","pi2fw","pmulhrw","pswapd"],"name":"3DNow!","summary":"3DNow!, AMD's floating-point extension for MMX registers, computes with two single-precision values packed into one register, with fast reciprocal approximations.","url":"https://x86-64.net/isa/3dnow/"},{"group":"memory","id":"prefetchw","isa_sets":["PREFETCH_NOP"],"mnemonics":["nop","prefetch","prefetchw"],"name":"PREFETCHW","summary":"PREFETCH and PREFETCHW, which came with 3DNow!, fetch a cache line ahead of a read or a write; every AMD64 processor has them, and Intel's processors have PREFETCHW.","url":"https://x86-64.net/isa/prefetchw/"},{"group":"vector","id":"sse4a","isa_sets":["SSE4a"],"mnemonics":["extrq","insertq","movntsd","movntss"],"name":"SSE4a","summary":"SSE4a, AMD's own addition to SSE3, extracts and inserts bit fields in XMM registers and stores scalar values non-temporally.","url":"https://x86-64.net/isa/sse4a/"},{"group":"vector","id":"xop","isa_sets":["XOP"],"mnemonics":["vfrczpd","vfrczps","vfrczsd","vfrczss","vpcmov","vpcomb","vpcomd","vpcomq","vpcomub","vpcomud","vpcomuq","vpcomuw","vpcomw","vpermil2pd","vpermil2ps","vphaddbd","vphaddbq","vphaddbw","vphadddq","vphaddubd","vphaddubq","vphaddubw","vphaddudq","vphadduwd","vphadduwq","vphaddwd","vphaddwq","vphsubbw","vphsubdq","vphsubwd","vpmacsdd","vpmacsdqh","vpmacsdql","vpmacssdd","vpmacssdqh","vpmacssdql","vpmacsswd","vpmacssww","vpmacswd","vpmacsww","vpmadcsswd","vpmadcswd","vpperm","vprotb","vprotd","vprotq","vprotw","vpshab","vpshad","vpshaq","vpshaw","vpshlb","vpshld","vpshlq","vpshlw"],"name":"XOP","summary":"XOP, the extended operations of AMD's Bulldozer family, adds integer multiply-accumulate, horizontal adds, shifts and rotates per element, compares with a predicate and byte permutes, in an encoding of its own.","url":"https://x86-64.net/isa/xop/"},{"group":"system","id":"lwp","isa_sets":["LWP"],"mnemonics":["llwpcb","lwpins","lwpval","slwpcb"],"name":"LWP","summary":"Lightweight Profiling (LWP) lets a program count and sample its own events into a ring buffer in memory, without entering the kernel.","url":"https://x86-64.net/isa/lwp/"},{"group":"vector","id":"fma4","isa_sets":["FMA4"],"mnemonics":["vfmaddpd","vfmaddps","vfmaddsd","vfmaddss","vfmaddsubpd","vfmaddsubps","vfmsubaddpd","vfmsubaddps","vfmsubpd","vfmsubps","vfmsubsd","vfmsubss","vfnmaddpd","vfnmaddps","vfnmaddsd","vfnmaddss","vfnmsubpd","vfnmsubps","vfnmsubsd","vfnmsubss"],"name":"FMA4","summary":"FMA4, AMD's fused multiply-add of the Bulldozer family, takes four operands, a separate destination and three sources, where FMA overwrites one of its three.","url":"https://x86-64.net/isa/fma4/"},{"group":"general","id":"tbm","isa_sets":["TBM"],"mnemonics":["bextr","blcfill","blci","blcic","blcmsk","blcs","blsfill","blsic","t1mskc","tzmsk"],"name":"TBM","summary":"Trailing Bit Manipulation (TBM) computes masks and fills around the lowest set or clear bit of a register in one instruction, and adds BEXTR with an immediate.","url":"https://x86-64.net/isa/tbm/"},{"group":"system","id":"svm","isa_sets":["SVM"],"mnemonics":["clgi","invlpga","skinit","stgi","vmload","vmmcall","vmrun","vmsave"],"name":"SVM","summary":"SVM, AMD's virtualization extension (AMD-V), runs a guest with VMRUN from a control block in memory, the VMCB, until an intercepted event returns control to the hypervisor.","url":"https://x86-64.net/isa/svm/"},{"group":"system","id":"sev-snp","isa_sets":["SNP"],"mnemonics":["psmash","pvalidate","rmpadjust","rmpupdate"],"name":"SEV-SNP","summary":"SEV-SNP, Secure Nested Paging, keeps a reverse map (RMP) of which guest owns each page, so that the hypervisor cannot remap or read the memory of an encrypted guest.","url":"https://x86-64.net/isa/sev-snp/"},{"group":"memory","id":"clzero","isa_sets":["CLZERO"],"mnemonics":["clzero"],"name":"CLZERO","summary":"CLZERO zeroes a whole cache line with one instruction.","url":"https://x86-64.net/isa/clzero/"},{"group":"system","id":"monitorx","isa_sets":["MONITORX"],"mnemonics":["monitorx","mwaitx"],"name":"MONITORX","summary":"MONITORX and MWAITX are AMD's MONITOR and MWAIT for every privilege level, with a timeout on the wait.","url":"https://x86-64.net/isa/monitorx/"},{"group":"memory","id":"mcommit","isa_sets":["MCOMMIT"],"mnemonics":["mcommit"],"name":"MCOMMIT","summary":"MCOMMIT waits until earlier stores to memory with delayed error reporting have completed and says in CF whether any of them failed.","url":"https://x86-64.net/isa/mcommit/"},{"group":"system","id":"rdpru","isa_sets":["RDPRU"],"mnemonics":["rdpru"],"name":"RDPRU","summary":"RDPRU lets programs read the MPERF and APERF counters, which measure the processor's effective frequency, without a system call.","url":"https://x86-64.net/isa/rdpru/"},{"group":"system","id":"invlpgb","isa_sets":["AMD_INVLPGB"],"mnemonics":["invlpgb","tlbsync"],"name":"INVLPGB","summary":"INVLPGB invalidates TLB entries on every processor of a system at once, without interrupts between processors, and TLBSYNC waits for them to finish.","url":"https://x86-64.net/isa/invlpgb/"},{"group":"crypto","id":"via-padlock","isa_sets":["VIA_PADLOCK_AES","VIA_PADLOCK_MONTMUL","VIA_PADLOCK_RNG","VIA_PADLOCK_SHA"],"mnemonics":["montmul","xcryptcbc","xcryptcfb","xcryptctr","xcryptecb","xcryptofb","xsha1","xsha256","xstore"],"name":"VIA PadLock","summary":"VIA's PadLock units encrypt with AES, hash with SHA-1 and SHA-256, generate random numbers and multiply for modular arithmetic, each instruction working through a whole buffer in memory.","url":"https://x86-64.net/isa/via-padlock/"}],"groups":[{"id":"general","name":"General-purpose"},{"id":"vector","name":"Vector (SSE, AVX and AVX10)"},{"id":"x87-mmx","name":"x87, MMX and 3DNow!"},{"id":"matrix","name":"Matrix (AMX and ACE)"},{"id":"crypto","name":"Cryptography"},{"id":"memory","name":"Memory, caches and atomics"},{"id":"system","name":"System"}],"isa_sets":{"3DNOW":{"chips":["AMD_K10"],"requirement":[[{"cpuid":"CPUID.80000001H:EDX[31]","name":"3DNow"}]]},"3DNOW_EXT":{"chips":["AMD_K10"],"requirement":[[{"cpuid":"CPUID.80000001H:EDX[30]","name":"3DNowExt"}]]},"ACE_1":{"chips":[],"requirement":[[{"cpuid":"CPUID.(EAX=07H,ECX=1):ECX[11]","name":"ACE"},{"cpuid":"CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1","name":"ACE version"}]]},"ADOX_ADCX":{"chips":["BROADWELL","SKYLAKE","COMET_LAKE","CANNONLAKE","ICE_LAKE","TIGER_LAKE","ALDER_LAKE","ARROW_LAKE","PANTHER_LAKE","NOVA_LAKE","SKYLAKE_SERVER","CASCADE_LAKE","COOPER_LAKE","ICE_LAKE_SERVER","SAPPHIRE_RAPIDS","EMERALD_RAPIDS","GRANITE_RAPIDS","DIAMOND_RAPIDS","SIERRA_FOREST","CLEARWATER_FOREST","KNL","KNM","AMD_ZEN","AMD_ZENPLUS","AMD_ZEN2","zen-3","zen-4","zen-5","zen-6"],"requirement":[[{"cpuid":"CPUID.(EAX=07H,ECX=0):EBX[19]","name":"ADX"}]]},"AES":{"chips":["WESTMERE","SANDYBRIDGE","IVYBRIDGE","HASWELL","BROADWELL","SKYLAKE","COMET_LAKE","CANNONLAKE","ICE_LAKE","TIGER_LAKE","ALDER_LAKE","ARROW_LAKE","PANTHER_LAKE","NOVA_LAKE","SKYLAKE_SERVER","CASCADE_LAKE","COOPER_LAKE","ICE_LAKE_SERVER","SAPPHIRE_RAPIDS","EMERALD_RAPIDS","GRANITE_RAPIDS","DIAMOND_RAPIDS","SILVERMONT","GOLDMONT","GOLDMONT_PLUS","TREMONT","SNOW_RIDGE","LAKEFIELD","SIERRA_FOREST","CLEARWATER_FOREST","KNL","KNM","AMD_K10","AMD_BULLDOZER","AMD_PILEDRIVER","AMD_ZEN","AMD_ZENPLUS","AMD_ZEN2","zen-3","zen-4","zen-5","zen-6"],"requirement":[[{"cpuid":"CPUID.01H:ECX[25]","name":"AES"}]]},"AMD":{"chips":["AMD_K10","AMD_BULLDOZER","AMD_PILEDRIVER","AMD_ZEN","AMD_ZENPLUS","AMD_ZEN2","zen-3","zen-4","zen-5","zen-6"],"requirement":[]},"AMD_INVLPGB":{"chips":["zen-3","zen-4","zen-5","zen-6"],"requirement":[[{"cpuid":"CPUID.80000008H:EBX[3]","name":"INVLPGB"}]]},"AMX_AVX512":{"chips":["DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=07H,ECX=1):ECX[11]","name":"ACE"},{"cpuid":"CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1","name":"ACE version"}],[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[7]","name":"AMX_AVX512"}]]},"AMX_BF16":{"chips":["SAPPHIRE_RAPIDS","EMERALD_RAPIDS","GRANITE_RAPIDS","DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[1]","name":"AMX_BF16 (leaf 1EH)"}],[{"cpuid":"CPUID.(EAX=07H,ECX=0):EDX[24]","name":"AMX_TILE"},{"cpuid":"CPUID.(EAX=07H,ECX=0):EDX[22]","name":"AMX_BF16"}]]},"AMX_COMPLEX":{"chips":["GRANITE_RAPIDS","DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[2]","name":"AMX_COMPLEX (leaf 1EH)"}],[{"cpuid":"CPUID.(EAX=07H,ECX=1):EDX[8]","name":"AMX_COMPLEX"}]]},"AMX_FP16":{"chips":["GRANITE_RAPIDS","DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[3]","name":"AMX_FP16 (leaf 1EH)"}],[{"cpuid":"CPUID.(EAX=07H,ECX=0):EDX[24]","name":"AMX_TILE"},{"cpuid":"CPUID.(EAX=07H,ECX=1):EAX[21]","name":"AMX_FP16"}]]},"AMX_FP8":{"chips":["DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[4]","name":"AMX_FP8"}]]},"AMX_INT8":{"chips":["SAPPHIRE_RAPIDS","EMERALD_RAPIDS","GRANITE_RAPIDS","DIAMOND_RAPIDS"],"requirement":[[{"cpuid":"CPUID.(EAX=1EH,ECX=1):EAX[0]","name":"AMX_INT8 (leaf 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a bit for each GETSEC leaf the processor supports and one for an Intel TXT chipset; any privilege level may run it.","url":"https://x86-64.net/insn/getsec-capabilities/","value":0},{"cpuid":null,"id":"getsec-enteraccs","instruction":"getsec","name":"GETSEC[ENTERACCS]","register":"EAX","summary":"Loads the authenticated code module at the physical address in EBX, checks its signature with the chipset's key and runs it.","url":"https://x86-64.net/insn/getsec-enteraccs/","value":2},{"cpuid":null,"id":"getsec-exitac","instruction":"getsec","name":"GETSEC[EXITAC]","register":"EAX","summary":"Leaves authenticated code execution mode and continues at the address in EBX; an authenticated code module ends with it.","url":"https://x86-64.net/insn/getsec-exitac/","value":3},{"cpuid":null,"id":"getsec-senter","instruction":"getsec","name":"GETSEC[SENTER]","register":"EAX","summary":"Launches a measured environment: authenticates the module at the physical address in EBX and gathers the other logical processors.","url":"https://x86-64.net/insn/getsec-senter/","value":4},{"cpuid":null,"id":"getsec-sexit","instruction":"getsec","name":"GETSEC[SEXIT]","register":"EAX","summary":"Ends the measured environment that SENTER launched, signalling every logical processor of the platform.","url":"https://x86-64.net/insn/getsec-sexit/","value":5},{"cpuid":null,"id":"getsec-parameters","instruction":"getsec","name":"GETSEC[PARAMETERS]","register":"EAX","summary":"Returns one SMX parameter per index in EBX, such as the versions of authenticated code modules that the processor accepts.","url":"https://x86-64.net/insn/getsec-parameters/","value":6},{"cpuid":null,"id":"getsec-smctrl","instruction":"getsec","name":"GETSEC[SMCTRL]","register":"EAX","summary":"Performs the SMX mode control that EBX selects; the only one, 0, unmasks SMIs after a measured launch.","url":"https://x86-64.net/insn/getsec-smctrl/","value":7},{"cpuid":null,"id":"getsec-wakeup","instruction":"getsec","name":"GETSEC[WAKEUP]","register":"EAX","summary":"Wakes the other logical processors from the sleep state that the SENTER rendezvous left them in, so that they join the measured environment.","url":"https://x86-64.net/insn/getsec-wakeup/","value":8},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"ecreate","instruction":"encls","name":"ECREATE","register":"EAX","summary":"Starts building an enclave by copying its control structure, the SECS, from ordinary memory into a page of the EPC.","url":"https://x86-64.net/insn/ecreate/","value":0},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"eadd","instruction":"encls","name":"EADD","register":"EAX","summary":"Copies a page from ordinary memory into the EPC for an enclave being built, and adds its offset and attributes to the enclave's measurement.","url":"https://x86-64.net/insn/eadd/","value":1},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"einit","instruction":"encls","name":"EINIT","register":"EAX","summary":"Completes the build of an enclave: checks its signed SIGSTRUCT and launch token, fixes its measurement and makes it ready for EENTER.","url":"https://x86-64.net/insn/einit/","value":2},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"eremove","instruction":"encls","name":"EREMOVE","register":"EAX","summary":"Removes a page from the EPC, detaching it from its enclave and marking it unused.","url":"https://x86-64.net/insn/eremove/","value":3},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"edbgrd","instruction":"encls","name":"EDBGRD","register":"EAX","summary":"Reads eight bytes (four outside 64-bit mode) of a debug enclave's memory, at the address in RCX, into RBX.","url":"https://x86-64.net/insn/edbgrd/","value":4},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"edbgwr","instruction":"encls","name":"EDBGWR","register":"EAX","summary":"Writes RBX (EBX outside 64-bit mode) to a debug enclave's memory at the address in RCX.","url":"https://x86-64.net/insn/edbgwr/","value":5},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"eextend","instruction":"encls","name":"EEXTEND","register":"EAX","summary":"Adds 256 bytes of a page of an enclave being built to the enclave's measurement, MRENCLAVE.","url":"https://x86-64.net/insn/eextend/","value":6},{"cpuid":{"cpuid":"CPUID.(EAX=12H,ECX=0):EAX[0]","name":"SGX1"},"id":"eldb","instruction":"encls","name":"ELDB","register":"EAX","summary":"Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and marks it 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