{ "features": [ { "cpuid": "CPUID.01H:EDX[15]", "description": "Conditional move.", "example": "cmov", "extra": false, "id": "cmov", "level": 1, "linux": "cmov", "name": "CMOV", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[8]", "description": "8-byte compare-and-exchange.", "example": "cmpxchg8b", "extra": false, "id": "cx8", "level": 1, "linux": "cx8", "name": "CX8", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[0]", "description": "x87 floating-point unit.", "example": "fld", "extra": false, "id": "fpu", "level": 1, "linux": "fpu", "name": "FPU", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[24]", "description": "FXSAVE and FXRSTOR, saving x87 and SSE state.", "example": "fxsave", "extra": false, "id": "fxsr", "level": 1, "linux": "fxsr", "name": "FXSR", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[23]", "description": "64-bit integer SIMD.", "example": "emms", "extra": false, "id": "mmx", "level": 1, "linux": "mmx", "name": "MMX", "os": false, "proxy": null }, { "cpuid": null, "description": "The OS has enabled FXSAVE/FXRSTOR and SSE (CR4.OSFXSR).", "example": "fxsave", "extra": false, "id": "osfxsr", "level": 1, "linux": null, "name": "OSFXSR", "os": true, "proxy": "fxsr" }, { "cpuid": "CPUID.80000001H:EDX[11]", "description": "SYSCALL and SYSRET fast system calls.", "example": "syscall", "extra": false, "id": "sce", "level": 1, "linux": "syscall", "name": "SCE", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[25]", "description": "128-bit single-precision SIMD.", "example": "cvtss2si", "extra": false, "id": "sse", "level": 1, "linux": "sse", "name": "SSE", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:EDX[26]", "description": "128-bit double-precision and integer SIMD.", "example": "cvtpi2pd", "extra": false, "id": "sse2", "level": 1, "linux": "sse2", "name": "SSE2", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[13]", "description": "16-byte compare-and-exchange, used for lock-free algorithms.", "example": "cmpxchg16b", "extra": false, "id": "cmpxchg16b", "level": 2, "linux": "cx16", "name": "CMPXCHG16B", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[0]", "description": "LAHF and SAHF in 64-bit mode.", "example": "lahf", "extra": false, "id": "lahf_sahf", "level": 2, "linux": "lahf_lm", "name": "LAHF-SAHF", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[23]", "description": "Population count (number of set bits).", "example": "popcnt", "extra": false, "id": "popcnt", "level": 2, "linux": "popcnt", "name": "POPCNT", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[0]", "description": "SSE3, shown as pni (\"Prescott New Instructions\") by Linux.", "example": "addsubpd", "extra": false, "id": "sse3", "level": 2, "linux": "pni", "name": "SSE3", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[19]", "description": "SSE4.1 blends, rounding, dot products and more.", "example": "blendpd", "extra": false, "id": "sse4_1", "level": 2, "linux": "sse4_1", "name": "SSE4.1", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[20]", "description": "SSE4.2 string comparison and CRC32.", "example": "pcmpestri", "extra": false, "id": "sse4_2", "level": 2, "linux": "sse4_2", "name": "SSE4.2", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[9]", "description": "Supplemental SSE3, including byte shuffles.", "example": "phaddd", "extra": false, "id": "ssse3", "level": 2, "linux": "ssse3", "name": "SSSE3", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[28]", "description": "256-bit floating-point SIMD with VEX encoding.", "example": "vzeroall", "extra": false, "id": "avx", "level": 3, "linux": "avx", "name": "AVX", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[5]", "description": "256-bit integer SIMD, gathers and permutes.", "example": "vpermd", "extra": false, "id": "avx2", "level": 3, "linux": "avx2", "name": "AVX2", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[3]", "description": "Bit manipulation instructions, group 1.", "example": "andn", "extra": false, "id": "bmi1", "level": 3, "linux": "bmi1", "name": "BMI1", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[8]", "description": "Bit manipulation instructions, group 2.", "example": "bzhi", "extra": false, "id": "bmi2", "level": 3, "linux": "bmi2", "name": "BMI2", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[29]", "description": "Half-precision float conversion.", "example": "vcvtph2ps", "extra": false, "id": "f16c", "level": 3, "linux": "f16c", "name": "F16C", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[12]", "description": "Fused multiply-add (three-operand FMA3).", "example": "vfmadd132pd", "extra": false, "id": "fma", "level": 3, "linux": "fma", "name": "FMA", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[5]", "description": "Leading zero count, shown as abm by Linux.", "example": "lzcnt", "extra": false, "id": "lzcnt", "level": 3, "linux": "abm", "name": "LZCNT", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[22]", "description": "Load or store with a byte swap.", "example": "movbe", "extra": false, "id": "movbe", "level": 3, "linux": "movbe", "name": "MOVBE", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[27]", "description": "The OS has enabled XSAVE, so AVX state is saved across context switches.", "example": "xgetbv", "extra": false, "id": "osxsave", "level": 3, "linux": null, "name": "OSXSAVE", "os": true, "proxy": "xsave" }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[16]", "description": "AVX-512 foundation.", "example": "kmovw", "extra": false, "id": "avx512f", "level": 4, "linux": "avx512f", "name": "AVX512F", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[30]", "description": "AVX-512 byte and word instructions.", "example": "vdbpsadbw", "extra": false, "id": "avx512bw", "level": 4, "linux": "avx512bw", "name": "AVX512BW", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[28]", "description": "AVX-512 conflict detection.", "example": "vplzcntd", "extra": false, "id": "avx512cd", "level": 4, "linux": "avx512cd", "name": "AVX512CD", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[17]", "description": "AVX-512 doubleword and quadword instructions.", "example": "vpmullq", "extra": false, "id": "avx512dq", "level": 4, "linux": "avx512dq", "name": "AVX512DQ", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[31]", "description": "AVX-512 instructions on 128- and 256-bit vectors.", "example": null, "extra": false, "id": "avx512vl", "level": 4, "linux": "avx512vl", "name": "AVX512VL", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[26]", "description": "XSAVE family of state save and restore instructions.", "example": "xsave", "extra": false, "id": "xsave", "level": null, "linux": "xsave", "name": "XSAVE", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[25]", "description": "AES encryption rounds.", "example": null, "extra": true, "id": "aes", "level": null, "linux": "aes", "name": "AES-NI", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[1]", "description": "Carry-less multiplication, used by GCM and CRC.", "example": null, "extra": true, "id": "pclmulqdq", "level": null, "linux": "pclmulqdq", "name": "PCLMULQDQ", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[29]", "description": "SHA-1 and SHA-256 acceleration.", "example": null, "extra": true, "id": "sha", "level": null, "linux": "sha_ni", "name": "SHA", "os": false, "proxy": null }, { "cpuid": "CPUID.01H:ECX[30]", "description": "Hardware random numbers.", "example": null, "extra": true, "id": "rdrand", "level": null, "linux": "rdrand", "name": "RDRAND", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[18]", "description": "Hardware random seeds.", "example": null, "extra": true, "id": "rdseed", "level": null, "linux": "rdseed", "name": "RDSEED", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[19]", "description": "ADCX and ADOX for multi-precision arithmetic.", "example": null, "extra": true, "id": "adx", "level": null, "linux": "adx", "name": "ADX", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[8]", "description": "Galois field arithmetic.", "example": null, "extra": true, "id": "gfni", "level": null, "linux": "gfni", "name": "GFNI", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[9]", "description": "AES on 256- and 512-bit vectors.", "example": null, "extra": true, "id": "vaes", "level": null, "linux": "vaes", "name": "VAES", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[10]", "description": "Carry-less multiplication on wide vectors.", "example": null, "extra": true, "id": "vpclmulqdq", "level": null, "linux": "vpclmulqdq", "name": "VPCLMULQDQ", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[6]", "description": "AMD-only SSE additions (EXTRQ, INSERTQ, MOVNTSD, MOVNTSS).", "example": null, "extra": true, "id": "sse4a", "level": null, "linux": "sse4a", "name": "SSE4a", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[16]", "description": "AMD four-operand fused multiply-add.", "example": null, "extra": true, "id": "fma4", "level": null, "linux": "fma4", "name": "FMA4", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[11]", "description": "AMD extended SIMD operations.", "example": null, "extra": true, "id": "xop", "level": null, "linux": "xop", "name": "XOP", "os": false, "proxy": null }, { "cpuid": "CPUID.80000001H:ECX[21]", "description": "AMD trailing bit manipulation.", "example": null, "extra": true, "id": "tbm", "level": null, "linux": "tbm", "name": "TBM", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EAX[4]", "description": "Dot-product instructions for neural networks, VEX-encoded.", "example": null, "extra": true, "id": "avx_vnni", "level": null, "linux": "avx_vnni", "name": "AVX-VNNI", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EAX[23]", "description": "52-bit integer multiply-add, VEX-encoded.", "example": null, "extra": true, "id": "avx_ifma", "level": null, "linux": null, "name": "AVX-IFMA", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EDX[4]", "description": "Dot products on 8-bit integers, VEX-encoded.", "example": null, "extra": true, "id": "avx_vnni_int8", "level": null, "linux": null, "name": "AVX-VNNI-INT8", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EBX[21]", "description": "52-bit integer multiply-add.", "example": null, "extra": true, "id": "avx512ifma", "level": null, "linux": "avx512ifma", "name": "AVX512-IFMA", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[1]", "description": "Byte permutes.", "example": null, "extra": true, "id": "avx512vbmi", "level": null, "linux": "avx512vbmi", "name": "AVX512-VBMI", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[6]", "description": "Byte and word compress, expand and shifts.", "example": null, "extra": true, "id": "avx512vbmi2", "level": null, "linux": "avx512_vbmi2", "name": "AVX512-VBMI2", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[11]", "description": "Dot-product instructions for neural networks.", "example": null, "extra": true, "id": "avx512vnni", "level": null, "linux": "avx512_vnni", "name": "AVX512-VNNI", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[12]", "description": "Bit counting on bytes and words.", "example": null, "extra": true, "id": "avx512bitalg", "level": null, "linux": "avx512_bitalg", "name": "AVX512-BITALG", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):ECX[14]", "description": "Population count on doublewords and quadwords.", "example": null, "extra": true, "id": "avx512vpopcntdq", "level": null, "linux": "avx512_vpopcntdq", "name": "AVX512-VPOPCNTDQ", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EAX[5]", "description": "bfloat16 conversions and dot products.", "example": null, "extra": true, "id": "avx512bf16", "level": null, "linux": "avx512_bf16", "name": "AVX512-BF16", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EDX[23]", "description": "Half-precision floating-point arithmetic.", "example": null, "extra": true, "id": "avx512fp16", "level": null, "linux": "avx512_fp16", "name": "AVX512-FP16", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EDX[8]", "description": "Intersection of doubleword and quadword vectors.", "example": null, "extra": true, "id": "avx512vp2intersect", "level": null, "linux": "avx512_vp2intersect", "name": "AVX512-VP2INTERSECT", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EDX[24]", "description": "Advanced Matrix Extensions tile registers.", "example": null, "extra": true, "id": "amx_tile", "level": null, "linux": "amx_tile", "name": "AMX-TILE", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EDX[25]", "description": "AMX 8-bit integer matrix multiply.", "example": null, "extra": true, "id": "amx_int8", "level": null, "linux": "amx_int8", "name": "AMX-INT8", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=0):EDX[22]", "description": "AMX bfloat16 matrix multiply.", "example": null, "extra": true, "id": "amx_bf16", "level": null, "linux": "amx_bf16", "name": "AMX-BF16", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EAX[21]", "description": "AMX half-precision matrix multiply.", "example": null, "extra": true, "id": "amx_fp16", "level": null, "linux": null, "name": "AMX-FP16", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EDX[19]", "description": "AVX10 version 1 (the version number is in CPUID leaf 24H).", "example": null, "extra": true, "id": "avx10_1", "level": null, "linux": null, "name": "AVX10.1", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EDX[19]", "description": "AVX10 version 2 (the version number is in CPUID leaf 24H).", "example": null, "extra": true, "id": "avx10_2", "level": null, "linux": null, "name": "AVX10.2", "os": false, "proxy": null }, { "cpuid": "CPUID.(EAX=07H,ECX=1):EDX[21]", "description": "Advanced Performance Extensions, including 32 general-purpose registers.", "example": null, "extra": true, "id": "apx_f", "level": null, "linux": null, "name": "APX", "os": false, "proxy": null } ], "levels": [ { "cumulative": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "osfxsr", "sce", "sse", "sse2" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "osfxsr", "sce", "sse", "sse2" ], "glibc_hwcaps": null, "id": "v1", "march": "x86-64", "name": "x86-64", "number": 1 }, { "cumulative": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "osfxsr", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3" ], "features": [ "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3" ], "glibc_hwcaps": "x86-64-v2", "id": "v2", "march": "x86-64-v2", "name": "x86-64-v2", "number": 2 }, { "cumulative": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "osfxsr", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "osxsave" ], "features": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "osxsave" ], "glibc_hwcaps": "x86-64-v3", "id": "v3", "march": "x86-64-v3", "name": "x86-64-v3", "number": 3 }, { "cumulative": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "osfxsr", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "osxsave", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl" ], "features": [ "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl" ], "glibc_hwcaps": "x86-64-v4", "id": "v4", "march": "x86-64-v4", "name": "x86-64-v4", "number": 4 } ], "license": "CC BY 4.0", "lines": [ { "id": "intel-client", "name": "Intel Core (client)" }, { "id": "intel-server", "name": "Intel Xeon (server)" }, { "id": "intel-atom", "name": "Intel Atom and E-cores" }, { "id": "intel-phi", "name": "Intel Xeon Phi" }, { "id": "amd-core", "name": "AMD (high performance)" }, { "id": "amd-cat", "name": "AMD (low power)" }, { "id": "hygon", "name": "Hygon" }, { "id": "zhaoxin", "name": "Zhaoxin" } ], "requirements": [ { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 3, "name": "AlmaLinux 10", "note": "AlmaLinux also publishes a separate x86_64_v2 build of AlmaLinux 10 for older processors.", "since": "10.0 (2025)", "sources": [ { "title": "AlmaLinux OS 10: usability without compromising compatibility", "url": "https://almalinux.org/blog/2025-05-27-welcoming-almalinux-10/" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 3, "name": "Red Hat Enterprise Linux 10", "note": null, "since": "10.0 (2025)", "sources": [ { "title": "Red Hat: Considerations in adopting RHEL 10, Architectures", "url": "https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/10/html/considerations_in_adopting_rhel_10/architectures" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 3, "name": "Rocky Linux 10", "note": null, "since": "10.0 (2025)", "sources": [ { "title": "Rocky Linux 10.0 available now", "url": "https://rockylinux.org/news/rocky-linux-10-0-ga-release" } ] }, { "checked": "2026-09-23", "exact": false, "features": [ "avx" ], "kind": "software", "level": 3, "name": "MongoDB", "note": "mongod and mongos need AVX, which puts the minimum between x86-64-v2 and x86-64-v3: Sandy Bridge and Bulldozer have it, but Pentium and Celeron models before Tiger Lake do not.", "since": "5.0 (2021)", "sources": [ { "title": "MongoDB: Production notes, x86_64 microarchitecture", "url": "https://www.mongodb.com/docs/manual/administration/production-notes/" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "runtime", "level": 2, "name": ".NET", "note": "Older processors fail with \"The current CPU is missing one or more of the baseline instruction sets\". ReadyToRun code in .NET 11 targets x86-64-v3 on Windows and Linux and falls back to the JIT on older processors.", "since": ".NET 11 (2026)", "sources": [ { "title": ".NET 11 breaking change: minimum hardware requirements (Microsoft)", "url": "https://learn.microsoft.com/en-us/dotnet/core/compatibility/jit/11/minimum-hardware-requirements" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 2, "name": "Red Hat Enterprise Linux 9", "note": null, "since": "9.0 (2022)", "sources": [ { "title": "Red Hat: Considerations in adopting RHEL 9, Architectures", "url": "https://docs.redhat.com/en/documentation/red_hat_enterprise_linux/9/html/considerations_in_adopting_rhel_9/ref_architectures_considerations-in-adopting-rhel-9" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 2, "name": "SUSE Linux Enterprise Server 16", "note": "The release notes add that QEMU guests need `-cpu host` (or another model with x86-64-v2 features) to boot.", "since": "16.0 (2025)", "sources": [ { "title": "SUSE Linux Enterprise Server 16.0 release notes", "url": "https://documentation.suse.com/releasenotes/sles/html/releasenotes_sles_16.0/index.html" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 2, "name": "Windows 11", "note": "Microsoft states that Windows 11 requires the x86-64-v2 instructions. Starting with version 24H2, Windows uses SSE4.2 and POPCNT and does not boot on processors without them.", "since": "24H2 (2024)", "sources": [ { "title": ".NET 11 breaking change: minimum hardware requirements (Microsoft)", "url": "https://learn.microsoft.com/en-us/dotnet/core/compatibility/jit/11/minimum-hardware-requirements" }, { "title": "Microsoft blocks some PCs from Windows 11 24H2: CPU must support SSE4.2 (Tom's Hardware)", "url": "https://www.tomshardware.com/software/windows/microsoft-updates-windows-11-24h2-requirements-cpu-must-support-sse42-or-the-os-will-not-boot" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 2, "name": "openSUSE Leap 16", "note": null, "since": "16.0 (2025)", "sources": [ { "title": "openSUSE Leap 16.0 release notes", "url": "https://doc.opensuse.org/release-notes/x86_64/openSUSE/Leap/16.0/html/release-notes-leap-160/index.html" } ] }, { "checked": "2026-09-23", "exact": true, "features": [], "kind": "os", "level": 1, "name": "Ubuntu", "note": "The default amd64 packages target the baseline. Since 25.10, Ubuntu also offers optional packages built for x86-64-v3 (the amd64v3 architecture variant).", "since": "all releases", "sources": [ { "title": "Ubuntu: Introducing architecture variants, amd64v3 now available in Ubuntu 25.10", "url": "https://discourse.ubuntu.com/t/introducing-architecture-variants-amd64v3-now-available-in-ubuntu-25-10/71312" } ] } ], "sources": { "features": [ { "title": "Linux arch/x86/include/asm/cpufeatures.h", "url": "https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/cpufeatures.h" }, { "title": "GCC gcc/config/i386/cpuid.h", "url": "https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h" } ], "levels": [ { "title": "System V Application Binary Interface, AMD64 Architecture Processor Supplement, Micro-Architecture Levels", "url": "https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex" } ] }, "uarch": [ { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": false }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": false } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "sse3" ], "id": "nocona", "level": 1, "line": "intel-client", "line_name": "Intel Core (client)", "march": "nocona", "min_level": 1, "name": "NetBurst (Prescott, Nocona)", "next_missing": [ "lahf_sahf", "popcnt", "sse4_1", "sse4_2", "ssse3" ], "notes": "Only the later NetBurst models implement Intel 64, and they lack LAHF/SAHF in 64-bit mode.", "products": "Pentium 4 and Pentium D models with Intel 64; Xeon (Nocona, Irwindale)", "sources": [ { "title": "GCC -march=nocona (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Pentium 4", "url": "https://en.wikipedia.org/wiki/Pentium_4" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2004 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "sse3", "ssse3" ], "id": "core2", "level": 1, "line": "intel-client", "line_name": "Intel Core (client)", "march": "core2", "min_level": 1, "name": "Core (Merom, Conroe)", "next_missing": [ "popcnt", "sse4_1", "sse4_2" ], "notes": null, "products": "Core 2 Duo and Core 2 Quad (Merom, Conroe, Kentsfield); Xeon 3000, 5100 and 7300", "sources": [ { "title": "GCC -march=core2 feature set (PTA_CORE2)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Intel Core (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2006 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "sse3", "sse4_1", "ssse3" ], "id": "penryn", "level": 1, "line": "intel-client", "line_name": "Intel Core (client)", "march": "core2", "min_level": 1, "name": "Penryn", "next_missing": [ "popcnt", "sse4_2" ], "notes": "Adds SSE4.1 to Core. GCC has no separate -march for Penryn; -march=core2 is the closest.", "products": "Core 2 Duo and Core 2 Quad (Penryn, Wolfdale, Yorkfield); Xeon 5200 and 5400", "sources": [ { "title": "Wikipedia: Penryn (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Penryn_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2007 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3" ], "id": "nehalem", "level": 2, "line": "intel-client", "line_name": "Intel Core (client)", "march": "nehalem", "min_level": 2, "name": "Nehalem", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave" ], "notes": null, "products": "Core i7 and i5 (Bloomfield, Lynnfield, Clarksfield); Xeon 3400, 5500 and 7500", "sources": [ { "title": "GCC -march=nehalem feature set (PTA_NEHALEM)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Nehalem (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2008 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "aes", "pclmulqdq" ], "id": "westmere", "level": 2, "line": "intel-client", "line_name": "Intel Core (client)", "march": "westmere", "min_level": 2, "name": "Westmere", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave" ], "notes": "Introduces AES-NI, which Intel did not enable on every model.", "products": "Core i3, i5 and i7 (Clarkdale, Arrandale, Gulftown); Xeon 5600 and E7", "sources": [ { "title": "GCC -march=westmere feature set (PTA_WESTMERE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Westmere (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Westmere_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2010 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": 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"extras": [ "aes", "pclmulqdq", "rdrand" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "rdrand" ], "id": "haswell", "level": 3, "line": "intel-client", "line_name": "Intel Core (client)", "march": "haswell", "min_level": 2, "name": "Haswell", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "4th generation Core; Xeon E3 v3, E5 v3 and E7 v3", "sources": [ { "title": "GCC -march=haswell feature set (PTA_HASWELL)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Haswell (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Haswell_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2013 }, { "checklist": [ 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"hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [ { "level": 2, "models": "Pentium and Celeron models", "note": "Intel sold these without AVX, and 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}, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq" ], "id": "rocket-lake", "level": 4, "line": "intel-client", "line_name": "Intel Core (client)", "march": "rocketlake", "min_level": 4, "name": "Rocket Lake", "next_missing": [], "notes": null, "products": "11th generation Core desktop processors; Xeon E-2300", "sources": [ { "title": "GCC -march=rocketlake feature set (PTA_ROCKETLAKE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Rocket Lake", "url": "https://en.wikipedia.org/wiki/Rocket_Lake" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2021 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": 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"present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Raptor Cove P-cores and Gracemont E-cores", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", 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true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Redwood Cove P-cores and Crestmont E-cores", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni" ], "id": "meteor-lake", "level": 3, "line": "intel-client", "line_name": "Intel Core (client)", "march": "meteorlake", "min_level": 3, "name": "Meteor Lake", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Core Ultra (Series 1)", "sources": [ { "title": "GCC -march=meteorlake (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Meteor Lake", "url": "https://en.wikipedia.org/wiki/Meteor_Lake" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2023 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Lion Cove P-cores and Skymont E-cores", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "id": "arrow-lake", "level": 3, "line": "intel-client", "line_name": "Intel Core (client)", "march": "arrowlake-s", "min_level": 3, "name": "Arrow Lake", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Core Ultra 200S, 200HX and 200H", "sources": [ { "title": "GCC -march=arrowlake-s feature set (PTA_ARROWLAKE_S)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Arrow Lake (microprocessor)", "url": "https://en.wikipedia.org/wiki/Arrow_Lake_(microprocessor)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2024 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Lion Cove P-cores and Skymont E-cores", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "id": "lunar-lake", "level": 3, "line": "intel-client", "line_name": "Intel Core (client)", "march": "lunarlake", "min_level": 3, "name": "Lunar Lake", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Core Ultra 200V", "sources": [ { "title": "GCC -march=lunarlake (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Lunar Lake", "url": "https://en.wikipedia.org/wiki/Lunar_Lake" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2024 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Cougar Cove P-cores and Darkmont E-cores", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "id": "panther-lake", "level": 3, "line": "intel-client", "line_name": "Intel Core (client)", "march": "pantherlake", "min_level": 3, "name": "Panther Lake", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Core Ultra (Series 3)", "sources": [ { "title": "GCC -march=pantherlake feature set (PTA_PANTHERLAKE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Panther Lake (microprocessor)", "url": "https://en.wikipedia.org/wiki/Panther_Lake_(microprocessor)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2026 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": "2027", "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "avx10_1", "avx10_2", "apx_f" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "avx10_1", "avx10_2", "apx_f" ], "id": "nova-lake", "level": 4, "line": "intel-client", "line_name": "Intel Core (client)", "march": "novalake", "min_level": 4, "name": "Nova Lake", "next_missing": [], "notes": "Intel has confirmed AVX10.2 and APX for Nova Lake. The feature list follows GCC's -march=novalake and may change before release.", "products": "Core Ultra 400 (announced)", "sources": [ { "title": "GCC -march=novalake feature set (PTA_NOVALAKE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Intel Officially Confirms AVX10.2 and APX Support in Nova Lake (TechPowerUp)", "url": "https://www.techpowerup.com/342881/intel-officially-confirms-avx10-2-and-apx-support-in-nova-lake" }, { "title": "Wikipedia: Nova Lake (microprocessor)", "url": "https://en.wikipedia.org/wiki/Nova_Lake_(microprocessor)" } ], "status": "announced", "updated": null, "vendor": "intel", "year": null }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "id": "skylake-sp", "level": 4, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "skylake-avx512", "min_level": 4, "name": "Skylake-SP", "next_missing": [], "notes": null, "products": "Xeon Scalable (1st generation); Core X-series (Skylake-X)", "sources": [ { "title": "GCC -march=skylake-avx512 feature set (PTA_SKYLAKE_AVX512)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Skylake (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Skylake_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2017 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vnni" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vnni" ], "id": "cascade-lake", "level": 4, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "cascadelake", "min_level": 4, "name": "Cascade Lake", "next_missing": [], "notes": null, "products": "2nd generation Xeon Scalable; Core X-series 10000", "sources": [ { "title": "GCC -march=cascadelake feature set (PTA_CASCADELAKE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Cascade Lake", "url": "https://en.wikipedia.org/wiki/Cascade_Lake" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2019 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vnni", "avx512bf16" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vnni", "avx512bf16" ], "id": "cooper-lake", "level": 4, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "cooperlake", "min_level": 4, "name": "Cooper Lake", "next_missing": [], "notes": null, "products": "3rd generation Xeon Scalable for 4- and 8-socket servers", "sources": [ { "title": "GCC -march=cooperlake feature set (PTA_COOPERLAKE)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Cooper Lake", "url": "https://en.wikipedia.org/wiki/Cooper_Lake" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2020 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx512ifma", 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"avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "amx_tile", "amx_int8", "amx_bf16" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "amx_tile", "amx_int8", "amx_bf16" ], "id": "sapphire-rapids", "level": 4, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "sapphirerapids", "min_level": 4, "name": "Sapphire Rapids", "next_missing": [], "notes": null, "products": "4th generation Xeon Scalable; Xeon W-2400 and W-3400", "sources": [ { "title": "GCC -march=sapphirerapids feature set (PTA_SAPPHIRERAPIDS)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Sapphire Rapids", "url": "https://en.wikipedia.org/wiki/Sapphire_Rapids" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2023 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "amx_tile", "amx_int8", "amx_bf16", "amx_fp16", "avx10_1" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "amx_tile", "amx_int8", "amx_bf16", "amx_fp16", "avx10_1" ], "id": "granite-rapids", "level": 4, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "graniterapids", "min_level": 4, "name": "Granite Rapids", "next_missing": [], "notes": null, "products": "Xeon 6 with P-cores (6900P, 6700P, 6500P)", "sources": [ { "title": "GCC -march=graniterapids feature set (PTA_GRANITERAPIDS)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Granite Rapids", "url": "https://en.wikipedia.org/wiki/Granite_Rapids" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2024 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Crestmont E-cores only", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "id": "sierra-forest", "level": 3, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "sierraforest", "min_level": 3, "name": "Sierra Forest", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Xeon 6 with E-cores (6700E)", "sources": [ { "title": "GCC -march=sierraforest feature set (PTA_SIERRAFOREST)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Sierra Forest", "url": "https://en.wikipedia.org/wiki/Sierra_Forest" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2024 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": "Darkmont E-cores only", "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8" ], "id": "clearwater-forest", "level": 3, "line": "intel-server", "line_name": "Intel Xeon (server)", "march": "clearwaterforest", "min_level": 3, "name": "Clearwater Forest", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Xeon 6+ with E-cores", "sources": [ { "title": "GCC -march=clearwaterforest feature set (PTA_CLEARWATERFOREST)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Clearwater Forest", "url": "https://en.wikipedia.org/wiki/Clearwater_Forest" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2026 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni", "avx_ifma", "avx_vnni_int8", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "amx_tile", "amx_int8", "amx_bf16", "amx_fp16", "avx10_1", "avx10_2", "apx_f" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", 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"https://www.intel.com/content/www/us/en/developer/articles/technical/next-gen-performance-gcc-15.html" } ], "status": "announced", "updated": null, "vendor": "intel", "year": null }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "sse3", "ssse3", "movbe" ], "id": "bonnell", "level": 1, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "bonnell", "min_level": 1, "name": "Bonnell", "next_missing": [ "popcnt", "sse4_1", "sse4_2" ], "notes": "Many Bonnell-based Atom models, such as the N270, do not implement Intel 64 at all.", "products": "First-generation Atom (Silverthorne, Diamondville, Pineview)", "sources": [ { "title": "GCC -march=bonnell feature set (PTA_BONNELL)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Bonnell (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2008 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "sse3", "ssse3", "movbe" ], "id": "saltwell", "level": 1, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "bonnell", "min_level": 1, "name": "Saltwell", "next_missing": [ "popcnt", "sse4_1", "sse4_2" ], "notes": "A die shrink of Bonnell with the same instruction set; GCC has no separate -march for it.", "products": "Atom N2000 and D2000 (Cedarview), Atom Z2000", "sources": [ { "title": "GCC -march=bonnell (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Bonnell (microarchitecture), third generation cores", "url": "https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)#Third_generation_cores" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2011 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "pclmulqdq", "rdrand" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "movbe", "pclmulqdq", "rdrand" ], "id": "silvermont", "level": 2, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "silvermont", "min_level": 2, "name": "Silvermont", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "xsave" ], "notes": null, "products": "Atom Z3000 (Bay Trail) and C2000; Celeron and Pentium J1000/N2000", "sources": [ { "title": "GCC -march=silvermont feature set (PTA_SILVERMONT)", "url": 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"hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "pclmulqdq", "rdrand" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "movbe", "pclmulqdq", "rdrand" ], "id": "airmont", "level": 2, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "silvermont", "min_level": 2, "name": "Airmont", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "xsave" ], "notes": "A die shrink of Silvermont with the same instruction set; GCC has no separate -march for it.", "products": "Atom x5 and x7 (Cherry Trail); Celeron and Pentium N3000/J3000 (Braswell)", "sources": [ { "title": "GCC -march=silvermont (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Airmont", "url": "https://en.wikipedia.org/wiki/Airmont" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2015 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed" ], "id": "goldmont", "level": 2, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "goldmont", "min_level": 2, "name": "Goldmont", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt" ], "notes": null, "products": "Celeron and Pentium N3350/J3455 (Apollo Lake); Atom C3000 (Denverton)", "sources": [ { "title": "GCC -march=goldmont feature set (PTA_GOLDMONT)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Goldmont", "url": "https://en.wikipedia.org/wiki/Goldmont" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2016 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed" ], "id": "goldmont-plus", "level": 2, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "goldmont-plus", "min_level": 2, "name": "Goldmont Plus", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt" ], "notes": null, "products": "Pentium Silver and Celeron J4000/N4000 (Gemini Lake)", "sources": [ { "title": "GCC -march=goldmont-plus feature set (PTA_GOLDMONT_PLUS)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Goldmont Plus", "url": "https://en.wikipedia.org/wiki/Goldmont_Plus" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2017 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "gfni" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "gfni" ], "id": "tremont", "level": 2, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "tremont", "min_level": 2, "name": "Tremont", "next_missing": [ "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt" ], "notes": null, "products": "Pentium Silver and Celeron N4500/N5000/N6000 (Jasper Lake); Atom x6000E (Elkhart Lake); Lakefield", "sources": [ { "title": "GCC -march=tremont feature set (PTA_TREMONT)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Tremont (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Tremont_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2020 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "avx_vnni" ], "id": "gracemont", "level": 3, "line": "intel-atom", "line_name": "Intel Atom and E-cores", "march": "gracemont", "min_level": 3, "name": "Gracemont", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": "The E-cores of Alder Lake and Raptor Lake, also sold alone as Alder Lake-N.", "products": "Intel N100, N200 and N300 and Core i3-N305 (Alder Lake-N); the E-cores of 12th to 14th generation Core", "sources": [ { "title": "GCC -march=gracemont (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Gracemont (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Gracemont_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2021 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512cd", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "id": "knights-landing", "level": 3, "line": "intel-phi", "line_name": "Intel Xeon Phi", "march": "knl", "min_level": 3, "name": "Knights Landing", "next_missing": [ "avx512bw", "avx512dq", "avx512vl" ], "notes": "Implements AVX-512 without the BW, DQ and VL subsets, so it does not reach x86-64-v4. GCC 15 removed -march=knl.", "products": "Xeon Phi x200", "sources": [ { "title": "GCC -march=knl feature set (PTA_KNL)", "url": "https://github.com/gcc-mirror/gcc/blob/2296fb82a4eb8a30c93820141c5e41202e813057/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Xeon Phi", "url": "https://en.wikipedia.org/wiki/Xeon_Phi" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2016 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vpopcntdq" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512cd", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx", "avx512vpopcntdq" ], "id": "knights-mill", "level": 3, "line": "intel-phi", "line_name": "Intel Xeon Phi", "march": "knm", "min_level": 3, "name": "Knights Mill", "next_missing": [ "avx512bw", "avx512dq", "avx512vl" ], "notes": "GCC 15 removed -march=knm.", "products": "Xeon Phi 72x5", "sources": [ { "title": "GCC -march=knm feature set (PTA_KNM)", "url": "https://github.com/gcc-mirror/gcc/blob/2296fb82a4eb8a30c93820141c5e41202e813057/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Xeon Phi", "url": "https://en.wikipedia.org/wiki/Xeon_Phi" } ], "status": "released", "updated": null, "vendor": "intel", "year": 2017 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": false }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": false }, { "hw": "popcnt", "id": "popcnt", "present": false }, { "hw": "sse3", "id": "sse3", "present": false }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": false } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": false }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2" ], "id": "k8", "level": 1, "line": "amd-core", "line_name": "AMD (high performance)", "march": "k8", "min_level": 1, "name": "K8 (Hammer)", "next_missing": [ "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3" ], "notes": "The first x86-64 processors. Later revisions add SSE3 (GCC's -march=k8-sse3) and LAHF/SAHF in 64-bit mode, but no K8 has SSSE3, so all of them stay at the baseline.", "products": "Athlon 64, Opteron, Turion 64 and 64-bit Sempron", "sources": [ { "title": "GCC -march=k8 (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: AMD K8", "url": "https://en.wikipedia.org/wiki/AMD_K8" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2003 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": false } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": false } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "lzcnt", "sse4a" ], "id": "k10", "level": 1, "line": "amd-core", "line_name": "AMD (high performance)", "march": "amdfam10", "min_level": 1, "name": "K10 (Family 10h)", "next_missing": [ "sse4_1", "sse4_2", "ssse3" ], "notes": "Has POPCNT and LZCNT but not SSSE3 or SSE4.1, so it stays at the baseline.", "products": "Phenom, Phenom II, Athlon II; Opteron (Barcelona, Shanghai, Istanbul)", "sources": [ { "title": "GCC -march=amdfam10 (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: AMD 10h", "url": "https://en.wikipedia.org/wiki/AMD_10h" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2007 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sse4a", "fma4", "xop" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "lzcnt", "xsave", "aes", "pclmulqdq", "sse4a", "fma4", "xop" ], "id": "bulldozer", "level": 2, "line": "amd-core", "line_name": "AMD (high performance)", "march": "bdver1", "min_level": 2, "name": "Bulldozer", "next_missing": [ "avx2", "bmi1", "bmi2", "f16c", "fma", "movbe" ], "notes": null, "products": "FX-4100, 6100 and 8100; Opteron 4200 and 6200", "sources": [ { "title": "GCC -march=bdver1 feature set (PTA_BDVER1)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Bulldozer (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Bulldozer_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2011 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sse4a", "fma4", "xop", "tbm" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "bmi1", "f16c", "fma", "lzcnt", "xsave", "aes", "pclmulqdq", "sse4a", "fma4", "xop", "tbm" ], "id": "piledriver", "level": 2, "line": "amd-core", "line_name": "AMD (high performance)", "march": "bdver2", "min_level": 2, "name": "Piledriver", "next_missing": [ "avx2", "bmi2", "movbe" ], "notes": "Has FMA, F16C and BMI1 but not AVX2, BMI2 or MOVBE, so it stops at x86-64-v2.", "products": "FX-4300, 6300 and 8300; A-series (Trinity, Richland); Opteron 4300 and 6300", "sources": [ { "title": "GCC -march=bdver2 feature set (PTA_BDVER2)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Piledriver (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Piledriver_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2012 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sse4a", "fma4", "xop", "tbm" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "bmi1", "f16c", "fma", "lzcnt", "xsave", "aes", "pclmulqdq", "sse4a", "fma4", "xop", "tbm" ], "id": "steamroller", "level": 2, "line": "amd-core", "line_name": "AMD (high performance)", "march": "bdver3", "min_level": 2, "name": "Steamroller", "next_missing": [ "avx2", "bmi2", "movbe" ], "notes": null, "products": "A-series (Kaveri, Godavari); Athlon X4 860K", "sources": [ { "title": "GCC -march=bdver3 feature set (PTA_BDVER3)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Steamroller (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Steamroller_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2014 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "sse4a", "fma4", "xop", "tbm" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "rdrand", "sse4a", "fma4", "xop", "tbm" ], "id": "excavator", "level": 3, "line": "amd-core", "line_name": "AMD (high performance)", "march": "bdver4", "min_level": 3, "name": "Excavator", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "A-series (Carrizo, Bristol Ridge); Athlon X4 845", "sources": [ { "title": "GCC -march=bdver4 feature set (PTA_BDVER4)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Excavator (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Excavator_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2015 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "sse4a" ], "id": "zen", "level": 3, "line": "amd-core", "line_name": "AMD (high performance)", "march": "znver1", "min_level": 3, "name": "Zen", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "Ryzen 1000; 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EPYC 9004 and 8004", "sources": [ { "title": "GCC -march=znver4 feature set (PTA_ZNVER4)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Zen 4", "url": "https://en.wikipedia.org/wiki/Zen_4" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2022 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "sse4a", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512vp2intersect" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "sse4a", "avx_vnni", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512vp2intersect" ], "id": "zen-5", "level": 4, "line": "amd-core", "line_name": "AMD (high performance)", "march": "znver5", "min_level": 4, "name": "Zen 5", "next_missing": [], "notes": null, "products": "Ryzen 9000; Ryzen AI 300; EPYC 9005", "sources": [ { "title": "GCC -march=znver5 feature set (PTA_ZNVER5)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Zen 5", "url": "https://en.wikipedia.org/wiki/Zen_5" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2024 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": true }, { "hw": "avx512bw", "id": "avx512bw", "present": true }, { "hw": "avx512cd", "id": "avx512cd", "present": true }, { "hw": "avx512dq", "id": "avx512dq", "present": true }, { "hw": "avx512vl", "id": "avx512vl", "present": true } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": "Q4 2026", "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "sse4a", "avx_vnni", "avx_ifma", "avx_vnni_int8", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "avx512vp2intersect" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "avx512f", "avx512bw", "avx512cd", "avx512dq", "avx512vl", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "gfni", "vaes", "vpclmulqdq", "sse4a", "avx_vnni", "avx_ifma", "avx_vnni_int8", "avx512ifma", "avx512vbmi", "avx512vbmi2", "avx512vnni", "avx512bitalg", "avx512vpopcntdq", "avx512bf16", "avx512fp16", "avx512vp2intersect" ], "id": "zen-6", "level": 4, "line": "amd-core", "line_name": "AMD (high performance)", "march": "znver6", "min_level": 4, "name": "Zen 6", "next_missing": [], "notes": "AMD announced the first Zen 6 processors, EPYC 9006 \"Venice\", for shipment in Q4 2026. The feature list follows GCC's -march=znver6.", "products": "EPYC 9006 (Venice), announced", "sources": [ { "title": "GCC -march=znver6 feature set (PTA_ZNVER6)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "AMD Announces 6th Gen EPYC Server Processors Powered by Zen 6 (TechPowerUp)", "url": "https://www.techpowerup.com/351000/amd-announces-6th-gen-epyc-server-processors-powered-by-zen-6-microarchitecture" }, { "title": "Wikipedia: Zen 6", "url": "https://en.wikipedia.org/wiki/Zen_6" } ], "status": "announced", "updated": null, "vendor": "amd", "year": null }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": false }, { "hw": "sse4_2", "id": "sse4_2", "present": false }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": false }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": false }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "ssse3", "lzcnt", "xsave", "sse4a" ], "id": "bobcat", "level": 1, "line": "amd-cat", "line_name": "AMD (low power)", "march": "btver1", "min_level": 1, "name": "Bobcat", "next_missing": [ "sse4_1", "sse4_2" ], "notes": "Lacks SSE4.1 and SSE4.2, so it stays at the baseline.", "products": "E-, C-, G- and Z-series APUs (for example E-350 and C-50)", "sources": [ { "title": "GCC -march=btver1 feature set (PTA_BTVER1)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Bobcat (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Bobcat_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2011 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "bmi1", "f16c", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sse4a" ], "id": "jaguar", "level": 2, "line": "amd-cat", "line_name": "AMD (low power)", "march": "btver2", "min_level": 2, "name": "Jaguar", "next_missing": [ "avx2", "bmi2", "fma" ], "notes": "Has AVX, F16C and MOVBE but not AVX2, FMA or BMI2, so it stops at x86-64-v2.", "products": "A4, A6, E1 and E2 APUs (Kabini, Temash); the PlayStation 4 and Xbox One", "sources": [ { "title": "GCC -march=btver2 feature set (PTA_BTVER2)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Jaguar (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Jaguar_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2013 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": false }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "bmi1", "f16c", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sse4a" ], "id": "puma", "level": 2, "line": "amd-cat", "line_name": "AMD (low power)", "march": "btver2", "min_level": 2, "name": "Puma", "next_missing": [ "avx2", "bmi2", "fma" ], "notes": "A revision of Jaguar with the same instruction set.", "products": "A-series and E-series APUs (Beema, Mullins)", "sources": [ { "title": "GCC -march=btver2 (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Puma (microarchitecture)", "url": "https://en.wikipedia.org/wiki/Puma_(microarchitecture)" } ], "status": "released", "updated": null, "vendor": "amd", "year": 2014 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "sse4a" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx", "sse4a" ], "id": "dhyana", "level": 3, "line": "hygon", "line_name": "Hygon", "march": "znver1", "min_level": 3, "name": "Dhyana", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": "Licensed from AMD's first-generation Zen and has the same instruction set.", "products": "Hygon C86 processors based on AMD's first-generation Zen", "sources": [ { "title": "GCC -march=znver1 (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Wikipedia: Hygon Information Technology", "url": "https://en.wikipedia.org/wiki/Hygon_Information_Technology" } ], "status": "released", "updated": null, "vendor": "hygon", "year": 2018 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": false }, { "hw": "avx2", "id": "avx2", "present": false }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": false }, { "hw": "fma", "id": "fma", "present": false }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "bmi1", "bmi2", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "rdrand", "rdseed", "adx" ], "id": "lujiazui", "level": 2, "line": "zhaoxin", "line_name": "Zhaoxin", "march": "lujiazui", "min_level": 2, "name": "LuJiaZui", "next_missing": [ "avx", "avx2", "f16c", "fma" ], "notes": "Has BMI1, BMI2 and MOVBE but no AVX, so it stops at x86-64-v2.", "products": "KX-6000 and KH-30000", "sources": [ { "title": "GCC -march=lujiazui feature set (PTA_LUJIAZUI)", "url": "https://github.com/gcc-mirror/gcc/blob/4b78815305fa285ad223f08b52128afdae782a62/gcc/config/i386/i386.h" }, { "title": "Wikipedia: Zhaoxin", "url": "https://en.wikipedia.org/wiki/Zhaoxin" } ], "status": "released", "updated": null, "vendor": "zhaoxin", "year": 2019 }, { "checklist": [ { "features": [ { "hw": "cmov", "id": "cmov", "present": true }, { "hw": "cx8", "id": "cx8", "present": true }, { "hw": "fpu", "id": "fpu", "present": true }, { "hw": "fxsr", "id": "fxsr", "present": true }, { "hw": "mmx", "id": "mmx", "present": true }, { "hw": "fxsr", "id": "osfxsr", "present": true }, { "hw": "sce", "id": "sce", "present": true }, { "hw": "sse", "id": "sse", "present": true }, { "hw": "sse2", "id": "sse2", "present": true } ], "number": 1 }, { "features": [ { "hw": "cmpxchg16b", "id": "cmpxchg16b", "present": true }, { "hw": "lahf_sahf", "id": "lahf_sahf", "present": true }, { "hw": "popcnt", "id": "popcnt", "present": true }, { "hw": "sse3", "id": "sse3", "present": true }, { "hw": "sse4_1", "id": "sse4_1", "present": true }, { "hw": "sse4_2", "id": "sse4_2", "present": true }, { "hw": "ssse3", "id": "ssse3", "present": true } ], "number": 2 }, { "features": [ { "hw": "avx", "id": "avx", "present": true }, { "hw": "avx2", "id": "avx2", "present": true }, { "hw": "bmi1", "id": "bmi1", "present": true }, { "hw": "bmi2", "id": "bmi2", "present": true }, { "hw": "f16c", "id": "f16c", "present": true }, { "hw": "fma", "id": "fma", "present": true }, { "hw": "lzcnt", "id": "lzcnt", "present": true }, { "hw": "movbe", "id": "movbe", "present": true }, { "hw": "xsave", "id": "osxsave", "present": true } ], "number": 3 }, { "features": [ { "hw": "avx512f", "id": "avx512f", "present": false }, { "hw": "avx512bw", "id": "avx512bw", "present": false }, { "hw": "avx512cd", "id": "avx512cd", "present": false }, { "hw": "avx512dq", "id": "avx512dq", "present": false }, { "hw": "avx512vl", "id": "avx512vl", "present": false } ], "number": 4 } ], "cores": null, "exceptions": [], "expected": null, "extras": [ "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx" ], "features": [ "cmov", "cx8", "fpu", "fxsr", "mmx", "sce", "sse", "sse2", "cmpxchg16b", "lahf_sahf", "popcnt", "sse3", "sse4_1", "sse4_2", "ssse3", "avx", "avx2", "bmi1", "bmi2", "f16c", "fma", "lzcnt", "movbe", "xsave", "aes", "pclmulqdq", "sha", "rdrand", "rdseed", "adx" ], "id": "century-avenue", "level": 3, "line": "zhaoxin", "line_name": "Zhaoxin", "march": "shijidadao", "min_level": 3, "name": "Century Avenue (Shijidadao)", "next_missing": [ "avx512bw", "avx512cd", "avx512dq", "avx512f", "avx512vl" ], "notes": null, "products": "KX-7000", "sources": [ { "title": "GCC -march=shijidadao (processor alias table)", "url": "https://github.com/gcc-mirror/gcc/blob/88d305a2de8bf5b7786c517f692e050082bb6787/gcc/common/config/i386/i386-common.cc" }, { "title": "Zhaoxin Launches KX-7000 Desktop 8-Core x86 Processor (TechPowerUp)", "url": "https://www.techpowerup.com/316685/zhaoxin-launches-kx-7000-desktop-8-core-x86-processor-to-power-chinas-ambitions" }, { "title": "Wikipedia: Zhaoxin", "url": "https://en.wikipedia.org/wiki/Zhaoxin" } ], "status": "released", "updated": null, "vendor": "zhaoxin", "year": 2023 } ] }