x86 instruction reference
x86 instructions from the general-purpose base to the newest extensions, with the syntax, encoding, CPUID requirement and processors of every form.
The reference covers the extensions listed under ISA extensions: the general-purpose instructions and the smaller sets around them, such as CMOV, BMI1 and CMPXCHG16B, and the recent extensions: APX, AVX10.1 and AVX10.2, the AMX family and ACE, the newer VEX extensions such as AVX-VNNI-INT8, SHA512, SM3 and SM4, and system instructions such as FRED and the new MSR instructions. Every mnemonic with a form in one of them has a page that lists all of its forms, including those of extensions not covered yet: VADDPS is here because AVX10.1 has it, and its page shows its AVX forms as well.
Syntax, encodings, CPUID bits and processor lists are generated from Intel XED, the encoder and decoder library that Intel publishes under the Apache License 2.0. The summary sentences and longer explanations are our own.
Instruction pages also list the C intrinsics that compile to the instruction, with the exact form each one compiles to, taken from Clang’s headers and checked by compiling every intrinsic. The x86 intrinsics A–Z index lists all of them.
| Mnemonic | Summary | Extensions |
|---|---|---|
| AAA | Corrects AL after adding two unpacked BCD digits: if the low digit exceeds 9 or AF is set, adds 6 to AL and 1 to AH and sets CF and AF; not in 64-bit mode. | General-purpose |
| AAD | Turns the unpacked BCD digits in AH and AL into the binary number AL plus AH times the immediate base (10 as assembled) before a DIV; not in 64-bit mode. | General-purpose |
| AADD | Atomically adds a register to a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAM | Splits AL into two unpacked BCD digits after a MUL: AH gets AL divided by the immediate base (10 as assembled), AL the remainder; not in 64-bit mode. | General-purpose |
| AAND | Atomically ANDs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAS | Corrects AL after subtracting two unpacked BCD digits: if the low digit exceeds 9 or AF is set, subtracts 6 from AX and 1 from AH; not in 64-bit mode. | General-purpose |
| ADC | Adds two integers and the carry flag, the step that chains multi-word additions; APX adds a three-operand form. | General-purpose, APX |
| ADCX | Adds two unsigned integers and the carry flag and changes only CF, so a carry chain can run next to an ADOX chain; APX adds a three-operand form. | ADX, APX |
| ADD | Adds two integers and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ADOX | Adds two unsigned integers and the overflow flag and changes only OF, so a carry chain can run next to an ADCX chain; APX adds a three-operand form. | ADX, APX |
| AND | Computes the bitwise AND of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ANDN | Computes the bitwise AND of the inverted first source with the second source into a separate destination; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| AOR | Atomically ORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AXOR | Atomically XORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| BEXTR | Extracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSI | Isolates the lowest set bit of the source, clearing all others; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSMSK | Sets all bits up to and including the lowest set bit of the source and clears the rest; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSR | Clears the lowest set bit of the source; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BOUND | Raises a bound-range exception (#BR) unless a signed array index in a register lies within the two bounds stored in memory; not in 64-bit mode. | General-purpose |
| BSF | Writes the index of the lowest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSR | Writes the index of the highest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSRINIT | ACE instruction that sets every byte of the block scale register to 7FH, the E8M0 encoding of a scale factor of 1.0. | ACE |
| BSRMOVF | ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half. | ACE |
| BSRMOVH | ACE instruction that moves the upper 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSRMOVL | ACE instruction that moves the lower 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSWAP | Reverses the byte order of a 32- or 64-bit register, converting between little- and big-endian values; with a 16-bit register the result is undefined. | General-purpose |
| BT | Copies the bit that a register or immediate offset selects in a register or memory operand into CF; a register offset can reach beyond a memory operand. | General-purpose |
| BTC | Copies the selected bit of a register or memory operand into CF and then inverts it; with LOCK the memory form is atomic. | General-purpose |
| BTR | Copies the selected bit of a register or memory operand into CF and then clears it; with LOCK the memory form is atomic. | General-purpose |
| BTS | Copies the selected bit of a register or memory operand into CF and then sets it; with LOCK the memory form is an atomic test-and-set. | General-purpose |
| BZHI | Clears the bits of the source from a given bit position upward; APX adds a form that leaves the flags unchanged. | BMI2, APX |
| CALL | Pushes the return address and jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| CBW | Sign-extends AL into AX, copying bit 7 of AL into every bit of AH (AT&T cbtw). | General-purpose |
| CCMPscc | APX conditional compare: if the flags meet a condition, compares two operands, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CDQ | Sign-extends EAX into EDX:EAX, filling EDX with the sign bit of EAX, typically before a 32-bit IDIV (AT&T cltd). | General-purpose |
| CDQE | Sign-extends EAX into RAX in 64-bit mode; compilers emit it, as cltq in AT&T syntax, to widen a signed 32-bit value. | General-purpose |
| CFCMOVcc | APX conditionally faulting move: on a false condition, memory is untouched and cannot fault; a register destination gets zero, or a source with NDD. | APX |
| CLC | Clears the carry flag (CF). | General-purpose |
| CLD | Clears the direction flag (DF), so that string instructions step upward through memory; the System V and Microsoft ABIs require it clear at calls. | General-purpose |
| CLDEMOTE | Hints that the cache line holding a byte of memory should move from the core's caches to a more distant level, where other cores reach it sooner. | CLDEMOTE |
| CLFLUSH | Writes back and invalidates the cache line holding a byte of memory in every cache of the coherence domain, ordered with writes and other CLFLUSHes. | CLFLUSH |
| CLFLUSHOPT | Writes back and invalidates the cache line holding a byte of memory like CLFLUSH, but unordered with flushes of other lines, so several can overlap. | CLFLUSHOPT |
| CLI | Clears the interrupt flag (IF) to hold off maskable interrupts; where CPL is above IOPL it faults or clears the virtual interrupt flag instead. | General-purpose |
| CLWB | Writes the cache line holding a byte of memory back if it was modified and may keep it cached, for example to make stores to persistent memory durable. | CLWB |
| CMC | Inverts the carry flag (CF). | General-purpose |
| CMOVcc | Copies the source to a register if a condition on the flags holds; APX adds a three-operand form that picks one of two sources. | CMOV, APX |
| CMP | Compares two operands by subtracting the second from the first, setting the arithmetic flags as SUB would and discarding the result. | General-purpose |
| CMPccXADD | Atomically compares memory with a register, adds a second register to memory if the condition holds, and returns the old value in the first. | CMPccXADD, APX |
| CMPS | Compares the element at [RSI] with the one at [RDI], setting the flags as CMP would, and steps both pointers; REPE and REPNE repeat it. | General-purpose |
| CMPXCHG | Compares the accumulator with the destination: if equal, stores the source there and sets ZF, else loads the destination; atomic with LOCK. | General-purpose |
| CMPXCHG16B | Compares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK. | CMPXCHG16B |
| CMPXCHG8B | Compares EDX:EAX with 8 bytes of memory: if equal, stores ECX:EBX there and sets ZF, else loads them into EDX:EAX; atomic with LOCK. | General-purpose |
| CPUID | Returns identification and feature information about the processor in EAX, EBX, ECX and EDX, for the leaf in EAX and the sub-leaf in ECX. | General-purpose |
| CQO | Sign-extends RAX into RDX:RAX, filling RDX with the sign bit of RAX, typically before a 64-bit IDIV (AT&T cqto); 64-bit mode only. | General-purpose |
| CRC32 | Accumulates a CRC-32C checksum (Castagnoli polynomial) over a 1-, 2-, 4- or 8-byte operand. | APX |
| CTESTscc | APX conditional test: if the flags meet a condition, tests two operands with AND, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CWD | Sign-extends AX into DX:AX, filling DX with the sign bit of AX, typically before a 16-bit IDIV (AT&T cwtd). | General-purpose |
| CWDE | Sign-extends AX into EAX (AT&T cwtl); in 64-bit mode the write to EAX also clears the upper half of RAX. | General-purpose |
| DAA | Corrects AL after adding two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal carry; not in 64-bit mode. | General-purpose |
| DAS | Corrects AL after subtracting two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal borrow; not in 64-bit mode. | General-purpose |
| DEC | Subtracts one from an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| DIV | Divides an unsigned double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| ENQCMD | Sends a 64-byte command, tagged with the PASID from the IA32_PASID MSR, to a device's enqueue register and sets ZF if the device did not accept it. | APX |
| ENQCMDS | Kernel version of ENQCMD that takes the PASID and privilege bit of the 64-byte command from its memory operand instead of the IA32_PASID MSR. | APX |
| ENTER | Makes a stack frame: pushes the frame pointer, copies outer frame pointers for nested procedures, and reserves the given bytes of locals. | General-purpose |
| ERETS | Returns from a FRED event handler to code that also runs in ring 0, restoring the interrupted context from the stack. | FRED |
| ERETU | Returns from a FRED event handler in ring 0 to ring 3, restoring the user context from the stack and swapping the GS base with IA32_KERNEL_GS_BASE. | FRED |
| HRESET | Resets the parts of the processor's prediction history that EAX selects and the operating system enabled in IA32_HRESET_ENABLE; allowed only in ring 0. | HRESET |
| IBHF | Indirect branch history fence: in ring 0 with BHI_DIS_S set, stops older branch history from steering later indirect branches; a no-op without BHI_CTRL. | IBHF |
| IDIV | Divides a signed double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| IMUL | Multiplies signed integers in one-, two- and three-operand forms; APX adds new-destination, flag-preserving and zero-upper immediate forms. | General-purpose, APX |
| IN | Reads a byte, word or doubleword from an I/O port, given as an immediate or in DX, into AL, AX or EAX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| INC | Adds one to an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| INS | Reads a byte, word or doubleword from the I/O port in DX into memory at [RDI] and steps RDI; REP repeats it RCX times. | General-purpose |
| INT | Raises the software interrupt whose vector is the immediate, calling its handler through the IDT, as 32-bit Linux system calls do with INT 80h. | General-purpose |
| INT1 | Raises a debug exception (#DB) with the one-byte opcode F1, meant for hardware debuggers; also known as ICEBP. | General-purpose |
| INT3 | Raises a breakpoint exception (#BP) with the one-byte opcode CC, which debuggers write over an instruction to set a breakpoint. | General-purpose |
| INTO | Raises an overflow exception (#OF) if the overflow flag is set; not in 64-bit mode. | General-purpose |
| INVEPT | Invalidates cached translations derived from a VMX guest's extended page tables, for one EPT context or all of them. | APX |
| INVPCID | Invalidates TLB entries and paging-structure caches for one address, one process-context identifier or all of them, as the type in a register selects. | APX |
| INVVPID | Invalidates cached translations tagged with a VMX virtual-processor identifier (VPID), for one address, one VPID or all of them. | APX |
| IRET | Returns from an interrupt or exception handler, popping the instruction pointer, CS and the flags, and in 64-bit mode RSP and SS too. | General-purpose |
| Jcc | Jumps to a relative target if a condition on the flags holds, such as JZ when ZF is set or JL when SF differs from OF. | General-purpose |
| JCXZ | Jumps to a short relative target if CX is zero, without testing or changing the flags; not in 64-bit mode. | General-purpose |
| JECXZ | Jumps to a short relative target if ECX is zero, without testing or changing the flags. | General-purpose |
| JMP | Jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| JMPABS | APX jump to a 64-bit absolute address given as an immediate, encoded with a REX2 prefix as an 11-byte instruction. | APX |
| JRCXZ | Jumps to a short relative target if RCX is zero, without testing or changing the flags; 64-bit mode only. | General-purpose |
| KADDB | Adds two 8-bit mask registers as unsigned integers. | AVX10.1 |
| KADDD | Adds two 32-bit mask registers as unsigned integers. | AVX10.1 |
| KADDQ | Adds two 64-bit mask registers as unsigned integers. | AVX10.1 |
| KADDW | Adds two 16-bit mask registers as unsigned integers. | AVX10.1 |
| KANDB | Computes the bitwise AND of two 8-bit masks. | AVX10.1 |
| KANDD | Computes the bitwise AND of two 32-bit masks. | AVX10.1 |
| KANDNB | Computes the bitwise AND of the inverted first 8-bit mask with the second. | AVX10.1 |
| KANDND | Computes the bitwise AND of the inverted first 32-bit mask with the second. | AVX10.1 |
| KANDNQ | Computes the bitwise AND of the inverted first 64-bit mask with the second. | AVX10.1 |
| KANDNW | Computes the bitwise AND of the inverted first 16-bit mask with the second. | AVX10.1 |
| KANDQ | Computes the bitwise AND of two 64-bit masks. | AVX10.1 |
| KANDW | Computes the bitwise AND of two 16-bit masks. | AVX10.1 |
| KMOVB | Moves an 8-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVD | Moves a 32-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVQ | Moves a 64-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVW | Moves a 16-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KNOTB | Inverts every bit of an 8-bit mask. | AVX10.1 |
| KNOTD | Inverts every bit of a 32-bit mask. | AVX10.1 |
| KNOTQ | Inverts every bit of a 64-bit mask. | AVX10.1 |
| KNOTW | Inverts every bit of a 16-bit mask. | AVX10.1 |
| KORB | Computes the bitwise OR of two 8-bit masks. | AVX10.1 |
| KORD | Computes the bitwise OR of two 32-bit masks. | AVX10.1 |
| KORQ | Computes the bitwise OR of two 64-bit masks. | AVX10.1 |
| KORTESTB | ORs two 8-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTD | ORs two 32-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTQ | ORs two 64-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTW | ORs two 16-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORW | Computes the bitwise OR of two 16-bit masks. | AVX10.1 |
| KSHIFTLB | Shifts an 8-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLD | Shifts a 32-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLQ | Shifts a 64-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLW | Shifts a 16-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRB | Shifts an 8-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRD | Shifts a 32-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRQ | Shifts a 64-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRW | Shifts a 16-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KTESTB | Sets ZF if the AND of two 8-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTD | Sets ZF if the AND of two 32-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTQ | Sets ZF if the AND of two 64-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTW | Sets ZF if the AND of two 16-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KUNPCKBW | Joins the low 8 bits of two masks into a 16-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKDQ | Joins the low 32 bits of two masks into a 64-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKWD | Joins the low 16 bits of two masks into a 32-bit mask, the second source forming the low half. | AVX10.1 |
| KXNORB | Computes the bitwise XNOR of two 8-bit masks. | AVX10.1 |
| KXNORD | Computes the bitwise XNOR of two 32-bit masks. | AVX10.1 |
| KXNORQ | Computes the bitwise XNOR of two 64-bit masks. | AVX10.1 |
| KXNORW | Computes the bitwise XNOR of two 16-bit masks. | AVX10.1 |
| KXORB | Computes the bitwise XOR of two 8-bit masks. | AVX10.1 |
| KXORD | Computes the bitwise XOR of two 32-bit masks. | AVX10.1 |
| KXORQ | Computes the bitwise XOR of two 64-bit masks. | AVX10.1 |
| KXORW | Computes the bitwise XOR of two 16-bit masks. | AVX10.1 |
| LAHF | Copies SF, ZF, AF, PF and CF into bits 7, 6, 4, 2 and 0 of AH; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| LDS | Loads a far pointer from memory into a register and DS; not in 64-bit mode, where its opcode C5 starts a VEX prefix. | General-purpose |
| LDTILECFG | Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers. | AMX-TILE, ACE, APX |
| LEA | Computes the address of a memory operand into a register without accessing memory, which compilers also use for arithmetic such as x*5+3. | General-purpose |
| LEAVE | Releases a stack frame: copies the frame pointer into the stack pointer, then pops the caller's frame pointer. | General-purpose |
| LES | Loads a far pointer from memory into a register and ES; not in 64-bit mode, where its opcode C4 starts a VEX prefix. | General-purpose |
| LFS | Loads a far pointer from memory into a register and FS. | General-purpose |
| LGS | Loads a far pointer from memory into a register and GS. | General-purpose |
| LKGS | Loads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only. | LKGS |
| LODS | Loads the element at [RSI] into AL, AX, EAX or RAX and steps RSI up or down, as the direction flag says. | General-purpose |
| LOOP | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero. | General-purpose |
| LOOPE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is set. | General-purpose |
| LOOPNE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is clear. | General-purpose |
| LSS | Loads a far pointer from memory into a register and SS, switching the stack segment and pointer with one instruction. | General-purpose |
| LZCNT | Counts the leading zero bits of an operand; APX adds a form that leaves the flags unchanged. | LZCNT, APX |
| MOV | Copies data between registers, memory and immediates, and moves segment, control and debug registers; those last two only in ring 0. | General-purpose |
| MOVBE | Loads or stores a 16-, 32- or 64-bit value with its byte order reversed; APX adds a register-to-register form. | MOVBE, APX |
| MOVDIR64B | Copies 64 bytes from memory to a 64-byte-aligned destination as one direct store that is written atomically and bypasses the caches. | APX |
| MOVDIRI | Stores a 32- or 64-bit register to memory as a direct store that bypasses the caches. | APX |
| MOVRS | Loads a register from memory with a hint that other cores are likely to read the same data before it is written. | MOVRS, APX |
| MOVS | Copies the element at [RSI] to [RDI] and steps both pointers; REP MOVS copies RCX elements, the classic memcpy. | General-purpose |
| MOVSX | Copies a signed byte or word into a wider register, extending its sign bit. | General-purpose |
| MOVSXD | Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode. | General-purpose |
| MOVZX | Copies an unsigned byte or word into a wider register, filling the upper bits with zeros. | General-purpose |
| MUL | Multiplies unsigned integers, producing a double-width result in rDX:rAX (AX for bytes); APX adds a form that leaves the flags unchanged. | General-purpose, APX |
| MULX | Multiplies rDX by an unsigned operand and writes the high and low halves of the product to two registers without touching the flags. | BMI2, APX |
| NEG | Replaces an operand with its two's complement; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| NOP | Does nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs. | General-purpose |
| NOT | Inverts every bit of an operand without changing the flags; APX adds a three-operand form. | General-purpose, APX |
| OR | Computes the bitwise OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| OUT | Writes AL, AX or EAX to an I/O port, given as an immediate or in DX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| OUTS | Writes a byte, word or doubleword from memory at [RSI] to the I/O port in DX and steps RSI; REP repeats it RCX times. | General-purpose |
| PAUSE | Tells the processor it is in a spin-wait loop, which avoids a penalty on leaving the loop and saves power; a NOP before the Pentium 4. | General-purpose |
| PBNDKB | Encrypts and authenticates a 256-byte bind structure with a platform key, for PCONFIG to use in configuring Total Storage Encryption. | PBNDKB |
| PDEP | Deposits the low bits of the source at the bit positions selected by a mask, clearing the others. | BMI2, APX |
| PEXT | Extracts the bits of the source at the positions selected by a mask and packs them into the low bits of the destination. | BMI2, APX |
| POP | Loads the value on top of the stack into a register, memory or a segment register and moves the stack pointer past it. | General-purpose |
| POP2 | APX instruction that pops two 64-bit registers from a 16-byte-aligned stack slot. | APX |
| POP2P | POP2 with APX's push-pop acceleration hint, marking it as the partner of a PUSH2P so the processor can forward the values without the memory round trip. | APX |
| POPA | Pops the eight general-purpose registers that PUSHA saved, 16-bit or with POPAD 32-bit, discarding the saved stack pointer; not in 64-bit mode. | General-purpose |
| POPCNT | Counts the bits that are set in an operand; APX adds a form that leaves the flags unchanged. | POPCNT, APX |
| POPF | Pops the flags from the stack, changing only those the privilege level allows; POPFQ, the 64-bit form, pops RFLAGS. | General-purpose |
| POPP | Pops a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of an earlier PUSHP. | APX |
| PREFETCHIT0 | Prefetches code at a RIP-relative address into all cache levels; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHIT1 | Prefetches code at a RIP-relative address into every cache level but L1; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHRST2 | Prefetches data with a hint that several cores are likely to read it before it is written, into caches chosen for read sharing. | MOVRS |
| PUSH | Moves the stack pointer down and stores a register, memory operand, immediate or segment register on top of the stack. | General-purpose |
| PUSH2 | APX instruction that pushes two 64-bit registers to a 16-byte-aligned stack slot. | APX |
| PUSH2P | PUSH2 with APX's push-pop acceleration hint, marking it as the partner of a POP2P so the processor can forward the values without the memory round trip. | APX |
| PUSHA | Pushes the eight 16-bit general-purpose registers, or with PUSHAD the 32-bit ones, including the original stack pointer; not in 64-bit mode. | General-purpose |
| PUSHF | Pushes the flags onto the stack: FLAGS, EFLAGS with PUSHFD, or RFLAGS with PUSHFQ, the default in 64-bit mode. | General-purpose |
| PUSHP | Pushes a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of a later POPP. | APX |
| RCL | Rotates an operand left through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RCR | Rotates an operand right through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RDMSR | Reads a model-specific register into EDX:EAX, or with MSR_IMM into any 64-bit register from an MSR number given as an immediate; allowed only in ring 0. | MSR_IMM, APX |
| RDMSRLIST | Reads up to 64 model-specific registers whose addresses are listed in a table in memory, selected by a bit mask in RCX, into a second table. | MSRLIST |
| RDPID | Reads the processor ID that the kernel stored in IA32_TSC_AUX (on Linux, the CPU and node number) without reading the time-stamp counter. | RDPID |
| RDRAND | Returns a random number from the processor's hardware generator; CF=1 means the value is valid, CF=0 that none was ready. | RDRAND |
| RDSEED | Returns a random number straight from the processor's entropy source, to seed other generators; CF=1 means the value is valid, CF=0 that none was ready. | RDSEED |
| RDTSCP | Reads the time-stamp counter into EDX:EAX and IA32_TSC_AUX into ECX, once all earlier instructions have executed. | RDTSCP |
| RET | Returns from a procedure: pops the return address (and CS for a far return) and optionally releases stack bytes of the caller's arguments. | General-purpose |
| ROL | Rotates an operand left; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ROR | Rotates an operand right; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| RORX | Rotates the source right by an immediate count into a separate destination without touching the flags. | BMI2, APX |
| SAHF | Stores bits 7, 6, 4, 2 and 0 of AH into SF, ZF, AF, PF and CF; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| SALC | Sets AL to FFh if the carry flag is set and to 00h if not, like SBB AL, AL but without changing the flags; not in 64-bit mode. | General-purpose |
| SAR | Shifts an operand right, copying the sign bit into the vacated bits; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SARX | Shifts the source right arithmetically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SBB | Subtracts an integer and the carry flag, the step that chains multi-word subtractions; APX adds a three-operand form. | General-purpose, APX |
| SCAS | Compares AL, AX, EAX or RAX with the element at [RDI], setting the flags as CMP would, and steps RDI; REPNE SCAS searches for a value. | General-purpose |
| SETcc | Writes 1 or 0 to a byte depending on a condition on the flags; APX adds a form that also clears the rest of the destination register. | General-purpose, APX |
| SHL | Shifts an operand left, filling with zeros (SAL is the same instruction); APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLD | Shifts an operand left and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLX | Shifts the source left by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SHR | Shifts an operand right, filling with zeros; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRD | Shifts an operand right and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRX | Shifts the source right logically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| STC | Sets the carry flag (CF). | General-purpose |
| STD | Sets the direction flag (DF), so that string instructions step downward through memory. | General-purpose |
| STI | Sets the interrupt flag (IF), accepting maskable interrupts after the next instruction; where CPL is above IOPL it faults or sets the virtual one instead. | General-purpose |
| STOS | Stores AL, AX, EAX or RAX at [RDI] and steps RDI; REP STOS fills RCX elements, the classic memset. | General-purpose |
| STTILECFG | Stores the current AMX tile configuration to a 64-byte memory block. | AMX-TILE, ACE, APX |
| SUB | Subtracts one integer from another and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| TCMMIMFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the imaginary parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCMMRLFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the real parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCVTROWD2PS | Moves one row of a tile to a ZMM register, converting its 32-bit integers to single precision. | AMX-AVX512, ACE |
| TCVTROWPS2BF16H | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2BF16L | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TCVTROWPS2PHH | Moves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2PHL | Moves one row of a tile to a ZMM register, converting single precision to half precision in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TDPBF16PS | Multiplies two tiles of bfloat16 pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-BF16 |
| TDPBF8PS | Multiplies two tiles of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBHF8PS | Multiplies a tile of E5M2 FP8 values by a tile of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBSSD | Multiplies two tiles of signed bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBSUD | Multiplies a tile of signed bytes by a tile of unsigned bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUSD | Multiplies a tile of unsigned bytes by a tile of signed bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUUD | Multiplies two tiles of unsigned bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPFP16PS | Multiplies two tiles of half-precision pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP16 |
| TDPHBF8PS | Multiplies a tile of E4M3 FP8 values by a tile of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPHF8PS | Multiplies two tiles of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TEST | ANDs two operands to set SF, ZF and PF and clear CF and OF, discarding the result; TEST with the same register twice checks it for zero. | General-purpose |
| TILELOADD | Loads a tile from memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILELOADDRS | Loads a tile from memory like TILELOADD, with a hint that other cores are likely to read the same data before it is written. | AMX-MOVRS, APX |
| TILELOADDRST1 | Loads a tile like TILELOADDRS, with the added hint that the data will be reused but need not stay in the nearest cache. | AMX-MOVRS, APX |
| TILELOADDT1 | Loads a tile like TILELOADD, with a hint that the data will be reused but need not stay in the nearest cache. | AMX-TILE, APX |
| TILEMOVCOL | ACE instruction that writes a ZMM register into one column of a tile register, the column chosen by an immediate or a register. | ACE |
| TILEMOVROW | Moves one row of a tile register to a ZMM register, or with ACE also the other way, the row chosen by an immediate or a register. | AMX-AVX512, ACE |
| TILERELEASE | Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero. | AMX-TILE, ACE |
| TILESTORED | Stores a tile to memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILEZERO | Sets every byte of a tile register to zero. | AMX-TILE, ACE |
| TOP2BF16PS | ACE rank-2 outer product: adds the dot product of each bfloat16 pair of one ZMM source with each pair of the other to a single-precision tile. | ACE |
| TOP4BSSD | ACE outer product of two ZMM registers of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BSUD | ACE outer product of a ZMM register of signed bytes with one of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUSD | ACE outer product of a ZMM register of unsigned bytes with one of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUUD | ACE outer product of two ZMM registers of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4MXBF8PS | ACE outer product of E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBHF8PS | ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBSSPS | ACE outer product of two ZMM registers of MX INT8 values, scaled by the block scale register and accumulated into a single-precision tile. | ACE |
| TOP4MXHBF8PS | ACE outer product of E4M3 by E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXHF8PS | ACE outer product of E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TZCNT | Counts the trailing zero bits of an operand; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| UD0 | Raises an invalid-opcode exception (#UD); some processors decode it without the ModR/M byte and operands that others read. | General-purpose |
| UD1 | Raises an invalid-opcode exception (#UD); its register and memory operands are decoded but not used. | General-purpose |
| UD2 | Raises an invalid-opcode exception (#UD); compilers emit it for __builtin_trap and code that must not be reached. | General-purpose |
| UDB | Raises an invalid-opcode exception (#UD) with the one-byte opcode D6, in 64-bit mode, where SALC is not available. | General-purpose |
| URDMSR | Reads a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| UWRMSR | Writes a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| VADDBF16 | Adds packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VADDPD | Adds packed doubles. | AVX10.1 |
| VADDPH | Adds packed half-precision values. | AVX10.1 |
| VADDPS | Adds packed singles. | AVX10.1 |
| VADDSD | Adds the low doubles; the other elements come from the first source. | AVX10.1 |
| VADDSH | Adds the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VADDSS | Adds the low singles; the other elements come from the first source. | AVX10.1 |
| VAESDEC | Performs one round of AES decryption on each 128-bit lane with the round key of the matching lane. | AVX10.1 |
| VAESDECLAST | Performs the last round of AES decryption on each 128-bit lane with the round key of the matching lane. | AVX10.1 |
| VAESENC | Performs one round of AES encryption on each 128-bit lane with the round key of the matching lane. | AVX10.1 |
| VAESENCLAST | Performs the last round of AES encryption on each 128-bit lane with the round key of the matching lane. | AVX10.1 |
| VALIGND | Concatenates two vectors and extracts one vector's worth of doublewords starting at an element offset given by an immediate. | AVX10.1 |
| VALIGNQ | Concatenates two vectors and extracts one vector's worth of quadwords starting at an element offset given by an immediate. | AVX10.1 |
| VANDNPD | Computes the bitwise AND of the inverted first source with the second, as packed doubles. | AVX10.1 |
| VANDNPS | Computes the bitwise AND of the inverted first source with the second, as packed singles. | AVX10.1 |
| VANDPD | Computes the bitwise AND of packed doubles. | AVX10.1 |
| VANDPS | Computes the bitwise AND of packed singles. | AVX10.1 |
| VBCSTNEBF162PS | Loads one bfloat16 value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBCSTNESH2PS | Loads one half-precision value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBLENDMPD | Picks each of the packed doubles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBLENDMPS | Picks each of the packed singles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBROADCASTF32X2 | Copies a group of two singles (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTF32X4 | Copies a group of four singles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF32X8 | Copies a group of eight singles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTF64X2 | Copies a group of two doubles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF64X4 | Copies a group of four doubles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI32X2 | Copies a group of two doublewords (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTI32X4 | Copies a group of four doublewords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI32X8 | Copies a group of eight doublewords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI64X2 | Copies a group of two quadwords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI64X4 | Copies a group of four quadwords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTSD | Copies one double from memory or an XMM register to every element of a vector. | AVX10.1 |
| VBROADCASTSS | Copies one single from memory or an XMM register to every element of a vector. | AVX10.1 |
| VCMPBF16 | Compares packed bfloat16 values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.2 |
| VCMPPD | Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VCMPPH | Compares packed half-precision values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VCMPPS | Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VCMPSD | Compares the low doubles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX10.1 |
| VCMPSH | Compares the low half-precision values with one of 32 predicates chosen by an immediate and writes the result to a mask register. | AVX10.1 |
| VCMPSS | Compares the low singles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX10.1 |
| VCOMISBF16 | Compares the low bfloat16 values of two registers and sets ZF, PF and CF as COMISS does, without floating-point exceptions. | AVX10.2 |
| VCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX10.1 |
| VCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX10.1 |
| VCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX10.1 |
| VCOMPRESSPD | Packs the doubles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMPRESSPS | Packs the singles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMXSD | Compares the low doubles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCOMXSH | Compares the low half-precision values and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation; NaNs signal invalid. | AVX10.2 |
| VCOMXSS | Compares the low singles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCVT2PH2BF8 | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2BF8S | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PH2HF8 | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2HF8S | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PS2PHX | Converts two vectors of single-precision values into one vector of half-precision values, rounding as MXCSR or the instruction selects. | AVX10.2 |
| VCVTBF162IBS | Converts packed bfloat16 values to signed bytes with saturation, rounding to nearest even, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF162IUBS | Converts packed bfloat16 values to saturated unsigned bytes, rounding to nearest even, each in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF42HF8 | Converts packed 4-bit E2M1 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF62HF8 | Converts packed 6-bit E3M2 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF82BF4S | Converts packed E5M2 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82BF6S | Converts packed E5M2 FP8 values to the 6-bit E3M2 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82PS | Converts packed E5M2 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTBIASPH2BF8 | Converts packed half-precision values to E5M2 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2BF8S | Converts packed half-precision values to E5M2 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPH2HF8 | Converts packed half-precision values to E4M3 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2HF8S | Converts packed half-precision values to E4M3 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPS2BF8 | Converts packed single-precision values to E5M2 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2BF8S | Converts packed single-precision values to E5M2 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTBIASPS2HF8 | Converts packed single-precision values to E4M3 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2HF8S | Converts packed single-precision values to E4M3 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTDQ2PD | Converts packed signed doublewords to doubles. | AVX10.1 |
| VCVTDQ2PH | Converts packed signed doublewords to half precision. | AVX10.1 |
| VCVTDQ2PS | Converts packed signed doublewords to singles. | AVX10.1 |
| VCVTHF62HF8 | Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTHF82BF4S | Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82HF6S | Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82PH | Converts packed E4M3 FP8 values to half precision, which is exact. | AVX10.2 |
| VCVTHF82PS | Converts packed E4M3 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTNE2PS2BF16 | Converts two vectors of singles into one vector of bfloat16 values, rounding to nearest even. | AVX10.1 |
| VCVTNEEBF162PS | Converts the even-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEEPH2PS | Converts the even-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOBF162PS | Converts the odd-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOPH2PS | Converts the odd-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEPS2BF16 | Converts packed single-precision values to bfloat16, rounding to nearest even with denormals flushed to zero and without consulting MXCSR. | AVX-NE-CONVERT, AVX10.1 |
| VCVTPD2DQ | Converts packed doubles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2PH | Converts packed doubles to half precision, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2PS | Converts packed doubles to singles, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2QQ | Converts packed doubles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UDQ | Converts packed doubles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UQQ | Converts packed doubles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2BF8 | Converts packed half-precision values to E5M2 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2BF8S | Converts packed half-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2DQ | Converts packed half-precision values to signed doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2HF8 | Converts packed half-precision values to E4M3 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2HF8S | Converts packed half-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2IBS | Converts packed half-precision values to signed bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2IUBS | Converts packed half-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2PD | Converts packed half-precision values to doubles, which is exact. | AVX10.1 |
| VCVTPH2PS | Converts packed half-precision values to singles, which is exact. | AVX10.1 |
| VCVTPH2PSX | Converts packed half-precision values to singles like VCVTPH2PS, in the AVX512-FP16 form that also takes a broadcast memory source. | AVX10.1 |
| VCVTPH2QQ | Converts packed half-precision values to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UDQ | Converts packed half-precision values to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UQQ | Converts packed half-precision values to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UW | Converts packed half-precision values to unsigned words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2W | Converts packed half-precision values to signed words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2BF8 | Converts packed single-precision values to E5M2 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2BF8S | Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2DQ | Converts packed singles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2HF8S | Converts packed single-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2IBS | Converts packed single-precision values to signed bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2IUBS | Converts packed single-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2PD | Converts packed singles to doubles, which is exact. | AVX10.1 |
| VCVTPS2PH | Converts packed singles to half precision, rounding as an immediate or MXCSR selects. | AVX10.1 |
| VCVTPS2PHX | Converts packed singles to half precision like VCVTPS2PH, but with a broadcast source and embedded rounding instead of an immediate. | AVX10.1 |
| VCVTPS2QQ | Converts packed singles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UDQ | Converts packed singles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UQQ | Converts packed singles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTQQ2PD | Converts packed signed quadwords to doubles. | AVX10.1 |
| VCVTQQ2PH | Converts packed signed quadwords to half precision. | AVX10.1 |
| VCVTQQ2PS | Converts packed signed quadwords to singles. | AVX10.1 |
| VCVTROPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again. | AVX10_V2_AUX |
| VCVTROPS2HF8S | Converts packed single-precision values to E4M3 FP8, rounding to odd and saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTSD2SH | Converts the low double of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSD2SS | Converts the low double of the second source to single, rounding as MXCSR or the instruction selects; the other elements come from the first source. | AVX10.1 |
| VCVTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SD | Converts the low half-precision value of the second source to double, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SS | Converts the low half-precision value of the second source to single, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2USI | Converts the low half-precision value to an unsigned integer in a 32- or 64-bit register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSI2SD | Converts a signed 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTSI2SH | Converts a signed 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTSI2SS | Converts a signed 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTSS2SD | Converts the low single of the second source to double, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSS2SH | Converts the low single of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTTBF162IBS | Converts packed bfloat16 values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTBF162IUBS | Converts packed bfloat16 values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPD2DQ | Converts packed doubles to signed doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPD2DQS | Converts packed doubles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2QQ | Converts packed doubles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2QQS | Converts packed doubles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UDQ | Converts packed doubles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UDQS | Converts packed doubles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UQQ | Converts packed doubles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UQQS | Converts packed doubles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPH2DQ | Converts packed half-precision values to signed doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2IBS | Converts packed half-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2IUBS | Converts packed half-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2QQ | Converts packed half-precision values to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UDQ | Converts packed half-precision values to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UQQ | Converts packed half-precision values to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UW | Converts packed half-precision values to unsigned words, truncating toward zero. | AVX10.1 |
| VCVTTPH2W | Converts packed half-precision values to signed words, truncating toward zero. | AVX10.1 |
| VCVTTPS2DQ | Converts packed singles to signed doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPS2DQS | Converts packed singles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2IBS | Converts packed single-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2IUBS | Converts packed single-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2QQ | Converts packed singles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2QQS | Converts packed singles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UDQ | Converts packed singles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UDQS | Converts packed singles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UQQ | Converts packed singles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UQQS | Converts packed singles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSD2SIS | Converts the low double to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSD2USIS | Converts the low double to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSH2USI | Converts the low half-precision value to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2SIS | Converts the low single to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2USIS | Converts the low single to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTUDQ2PD | Converts packed unsigned doublewords to doubles. | AVX10.1 |
| VCVTUDQ2PH | Converts packed unsigned doublewords to half precision. | AVX10.1 |
| VCVTUDQ2PS | Converts packed unsigned doublewords to singles. | AVX10.1 |
| VCVTUQQ2PD | Converts packed unsigned quadwords to doubles. | AVX10.1 |
| VCVTUQQ2PH | Converts packed unsigned quadwords to half precision. | AVX10.1 |
| VCVTUQQ2PS | Converts packed unsigned quadwords to singles. | AVX10.1 |
| VCVTUSI2SD | Converts an unsigned 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SH | Converts an unsigned 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SS | Converts an unsigned 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUW2PH | Converts packed unsigned words to half precision. | AVX10.1 |
| VCVTW2PH | Converts packed signed words to half precision. | AVX10.1 |
| VDBPSADBW | Sums absolute differences of 4-byte groups of the two sources into 16-bit results, after an immediate shuffles the second within each 128-bit lane. | AVX10.1 |
| VDIVBF16 | Divides packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VDIVPD | Divides packed doubles. | AVX10.1 |
| VDIVPH | Divides packed half-precision values. | AVX10.1 |
| VDIVPS | Divides packed singles. | AVX10.1 |
| VDIVSD | Divides the low doubles; the other elements come from the first source. | AVX10.1 |
| VDIVSH | Divides the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VDIVSS | Divides the low singles; the other elements come from the first source. | AVX10.1 |
| VDPBF16PS | Multiplies pairs of bfloat16 values and adds both products to the matching single-precision accumulator. | AVX10.1 |
| VDPPHPS | Multiplies pairs of half-precision values and adds both products to the matching single-precision accumulator. | AVX10.2 |
| VEXPANDPD | Spreads consecutive doubles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXPANDPS | Spreads consecutive singles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXTRACTF32X4 | Copies the 128-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF32X8 | Copies the 256-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X2 | Copies the 128-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X4 | Copies the 256-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI32X4 | Copies the 128-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI32X8 | Copies the 256-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X2 | Copies the 128-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X4 | Copies the 256-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTPS | Copies the single that an immediate selects from an XMM register to a general-purpose register or memory. | AVX10.1 |
| VFCMADDCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source and adds the products to the destination. | AVX10.1 |
| VFCMADDCSH | Multiplies the low complex half-precision number of the first source by the conjugate of the second's and adds the product to the destination. | AVX10.1 |
| VFCMULCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source. | AVX10.1 |
| VFCMULCSH | Multiplies the low complex half-precision number of the first source by the complex conjugate of the second source's. | AVX10.1 |
| VFIXUPIMMPD | Replaces special doubles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMPS | Replaces special singles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSD | Replaces a special low double (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSS | Replaces a special low single (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFMADD132BF16 | Fused multiply-add of packed bfloat16 values: first operand times third plus second, into the first. | AVX10.2 |
| VFMADD132PD | Fused multiply-add of packed doubles: first operand times third plus second, into the first. | AVX10.1 |
| VFMADD132PH | Fused multiply-add of packed half-precision values: first operand times third plus second, into the first. | AVX10.1 |
| VFMADD132PS | Fused multiply-add of packed singles: first operand times third plus second, into the first. | AVX10.1 |
| VFMADD132SD | Fused multiply-add of the low doubles: first times third plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD132SH | Fused multiply-add of the low half-precision values: first times third plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD132SS | Fused multiply-add of the low singles: first times third plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD213BF16 | Fused multiply-add of packed bfloat16 values: second operand times first plus third, into the first. | AVX10.2 |
| VFMADD213PD | Fused multiply-add of packed doubles: second operand times first plus third, into the first. | AVX10.1 |
| VFMADD213PH | Fused multiply-add of packed half-precision values: second operand times first plus third, into the first. | AVX10.1 |
| VFMADD213PS | Fused multiply-add of packed singles: second operand times first plus third, into the first. | AVX10.1 |
| VFMADD213SD | Fused multiply-add of the low doubles: second times first plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD213SH | Fused multiply-add of the low half-precision values: second times first plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD213SS | Fused multiply-add of the low singles: second times first plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD231BF16 | Fused multiply-add of packed bfloat16 values: second operand times third plus first, into the first. | AVX10.2 |
| VFMADD231PD | Fused multiply-add of packed doubles: second operand times third plus first, into the first. | AVX10.1 |
| VFMADD231PH | Fused multiply-add of packed half-precision values: second operand times third plus first, into the first. | AVX10.1 |
| VFMADD231PS | Fused multiply-add of packed singles: second operand times third plus first, into the first. | AVX10.1 |
| VFMADD231SD | Fused multiply-add of the low doubles: second times third plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD231SH | Fused multiply-add of the low half-precision values: second times third plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD231SS | Fused multiply-add of the low singles: second times third plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMADDCPH | Multiplies packed complex numbers, each a pair of half-precision values, and adds the products to the destination. | AVX10.1 |
| VFMADDCSH | Multiplies the low complex numbers, each a pair of half-precision values, and adds the product to the destination. | AVX10.1 |
| VFMADDSUB132PD | Fused multiply of packed doubles, first times third, minus the second in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB132PH | Fused multiply of packed half-precision values, first times third, minus the second in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB132PS | Fused multiply of packed singles, first times third, minus the second in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB213PD | Fused multiply of packed doubles, second times first, minus the third in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB213PH | Fused multiply of packed half-precision values, second times first, minus the third in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB213PS | Fused multiply of packed singles, second times first, minus the third in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB231PD | Fused multiply of packed doubles, second times third, minus the first in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB231PH | Fused multiply of packed half-precision values, second times third, minus the first in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB231PS | Fused multiply of packed singles, second times third, minus the first in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMSUB132BF16 | Fused multiply-subtract of packed bfloat16 values: first operand times third minus second, into the first. | AVX10.2 |
| VFMSUB132PD | Fused multiply-subtract of packed doubles: first operand times third minus second, into the first. | AVX10.1 |
| VFMSUB132PH | Fused multiply-subtract of packed half-precision values: first operand times third minus second, into the first. | AVX10.1 |
| VFMSUB132PS | Fused multiply-subtract of packed singles: first operand times third minus second, into the first. | AVX10.1 |
| VFMSUB132SD | Fused multiply-subtract of the low doubles: first times third minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB132SH | Fused multiply-subtract of the low half-precision values: first times third minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB132SS | Fused multiply-subtract of the low singles: first times third minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB213BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times first minus third, into the first. | AVX10.2 |
| VFMSUB213PD | Fused multiply-subtract of packed doubles: second operand times first minus third, into the first. | AVX10.1 |
| VFMSUB213PH | Fused multiply-subtract of packed half-precision values: second operand times first minus third, into the first. | AVX10.1 |
| VFMSUB213PS | Fused multiply-subtract of packed singles: second operand times first minus third, into the first. | AVX10.1 |
| VFMSUB213SD | Fused multiply-subtract of the low doubles: second times first minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB213SH | Fused multiply-subtract of the low half-precision values: second times first minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB213SS | Fused multiply-subtract of the low singles: second times first minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB231BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times third minus first, into the first. | AVX10.2 |
| VFMSUB231PD | Fused multiply-subtract of packed doubles: second operand times third minus first, into the first. | AVX10.1 |
| VFMSUB231PH | Fused multiply-subtract of packed half-precision values: second operand times third minus first, into the first. | AVX10.1 |
| VFMSUB231PS | Fused multiply-subtract of packed singles: second operand times third minus first, into the first. | AVX10.1 |
| VFMSUB231SD | Fused multiply-subtract of the low doubles: second times third minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB231SH | Fused multiply-subtract of the low half-precision values: second times third minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB231SS | Fused multiply-subtract of the low singles: second times third minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUBADD132PD | Fused multiply of packed doubles, first times third, plus the second in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD132PH | Fused multiply of packed half-precision values, first times third, plus the second in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD132PS | Fused multiply of packed singles, first times third, plus the second in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD213PD | Fused multiply of packed doubles, second times first, plus the third in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD213PH | Fused multiply of packed half-precision values, second times first, plus the third in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD213PS | Fused multiply of packed singles, second times first, plus the third in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD231PD | Fused multiply of packed doubles, second times third, plus the first in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD231PH | Fused multiply of packed half-precision values, second times third, plus the first in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD231PS | Fused multiply of packed singles, second times third, plus the first in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMULCPH | Multiplies packed complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFMULCSH | Multiplies the low complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFNMADD132BF16 | Fused negated multiply-add of packed bfloat16 values: minus first operand times third, plus second, into the first. | AVX10.2 |
| VFNMADD132PD | Fused negated multiply-add of packed doubles: minus first operand times third, plus second, into the first. | AVX10.1 |
| VFNMADD132PH | Fused negated multiply-add of packed half-precision values: minus first operand times third, plus second, into the first. | AVX10.1 |
| VFNMADD132PS | Fused negated multiply-add of packed singles: minus first operand times third, plus second, into the first. | AVX10.1 |
| VFNMADD132SD | Fused negated multiply-add of the low doubles: minus first times third, plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD132SH | Fused negated multiply-add of the low half-precision values: minus first times third, plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD132SS | Fused negated multiply-add of the low singles: minus first times third, plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD213BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times first, plus third, into the first. | AVX10.2 |
| VFNMADD213PD | Fused negated multiply-add of packed doubles: minus second operand times first, plus third, into the first. | AVX10.1 |
| VFNMADD213PH | Fused negated multiply-add of packed half-precision values: minus second operand times first, plus third, into the first. | AVX10.1 |
| VFNMADD213PS | Fused negated multiply-add of packed singles: minus second operand times first, plus third, into the first. | AVX10.1 |
| VFNMADD213SD | Fused negated multiply-add of the low doubles: minus second times first, plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD213SH | Fused negated multiply-add of the low half-precision values: minus second times first, plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD213SS | Fused negated multiply-add of the low singles: minus second times first, plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD231BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times third, plus first, into the first. | AVX10.2 |
| VFNMADD231PD | Fused negated multiply-add of packed doubles: minus second operand times third, plus first, into the first. | AVX10.1 |
| VFNMADD231PH | Fused negated multiply-add of packed half-precision values: minus second operand times third, plus first, into the first. | AVX10.1 |
| VFNMADD231PS | Fused negated multiply-add of packed singles: minus second operand times third, plus first, into the first. | AVX10.1 |
| VFNMADD231SD | Fused negated multiply-add of the low doubles: minus second times third, plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD231SH | Fused negated multiply-add of the low half-precision values: minus second times third, plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD231SS | Fused negated multiply-add of the low singles: minus second times third, plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB132BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus first operand times third, minus second, into the first. | AVX10.2 |
| VFNMSUB132PD | Fused negated multiply-subtract of packed doubles: minus first operand times third, minus second, into the first. | AVX10.1 |
| VFNMSUB132PH | Fused negated multiply-subtract of packed half-precision values: minus first operand times third, minus second, into the first. | AVX10.1 |
| VFNMSUB132PS | Fused negated multiply-subtract of packed singles: minus first operand times third, minus second, into the first. | AVX10.1 |
| VFNMSUB132SD | Fused negated multiply-subtract of the low doubles: minus first times third, minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB132SH | Fused negated multiply-subtract of the low half-precision values: minus first times third, minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB132SS | Fused negated multiply-subtract of the low singles: minus first times third, minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB213BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times first, minus third, into the first. | AVX10.2 |
| VFNMSUB213PD | Fused negated multiply-subtract of packed doubles: minus second operand times first, minus third, into the first. | AVX10.1 |
| VFNMSUB213PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times first, minus third, into the first. | AVX10.1 |
| VFNMSUB213PS | Fused negated multiply-subtract of packed singles: minus second operand times first, minus third, into the first. | AVX10.1 |
| VFNMSUB213SD | Fused negated multiply-subtract of the low doubles: minus second times first, minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB213SH | Fused negated multiply-subtract of the low half-precision values: minus second times first, minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB213SS | Fused negated multiply-subtract of the low singles: minus second times first, minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB231BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times third, minus first, into the first. | AVX10.2 |
| VFNMSUB231PD | Fused negated multiply-subtract of packed doubles: minus second operand times third, minus first, into the first. | AVX10.1 |
| VFNMSUB231PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times third, minus first, into the first. | AVX10.1 |
| VFNMSUB231PS | Fused negated multiply-subtract of packed singles: minus second operand times third, minus first, into the first. | AVX10.1 |
| VFNMSUB231SD | Fused negated multiply-subtract of the low doubles: minus second times third, minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB231SH | Fused negated multiply-subtract of the low half-precision values: minus second times third, minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB231SS | Fused negated multiply-subtract of the low singles: minus second times third, minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFPCLASSBF16 | Tests packed bfloat16 values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.2 |
| VFPCLASSPD | Tests packed doubles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPH | Tests packed half-precision values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPS | Tests packed singles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSSD | Tests the low double for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSH | Tests the low half-precision value for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSS | Tests the low single for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VGATHERDPD | Loads doubles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VGATHERDPS | Loads singles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VGATHERQPD | Loads doubles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VGATHERQPS | Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VGETEXPBF16 | Extracts the unbiased exponent of each packed bfloat16 value as a bfloat16 number. | AVX10.2 |
| VGETEXPPD | Extracts the unbiased exponent of packed doubles as floating-point numbers. | AVX10.1 |
| VGETEXPPH | Extracts the unbiased exponent of packed half-precision values as floating-point numbers. | AVX10.1 |
| VGETEXPPS | Extracts the unbiased exponent of packed singles as floating-point numbers. | AVX10.1 |
| VGETEXPSD | Extracts the unbiased exponent of the low double of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETEXPSH | Extracts the unbiased exponent of the low half-precision value of the second source as a float; the other elements come from the first source. | AVX10.1 |
| VGETEXPSS | Extracts the unbiased exponent of the low single of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETMANTBF16 | Extracts the normalized mantissa of each packed bfloat16 value, with the interval and sign handling chosen by an immediate. | AVX10.2 |
| VGETMANTPD | Extracts the normalized mantissa of packed doubles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPH | Extracts the normalized mantissa of packed half-precision values, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPS | Extracts the normalized mantissa of packed singles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTSD | Extracts the normalized mantissa of the low double of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGETMANTSH | Extracts the normalized mantissa of the low half-precision value of the second source, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VGETMANTSS | Extracts the normalized mantissa of the low single of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGF2P8AFFINEINVQB | Replaces each byte with its inverse in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant. | AVX10.1 |
| VGF2P8AFFINEQB | Applies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant. | AVX10.1 |
| VGF2P8MULB | Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1. | AVX10.1 |
| VINSERTF32X4 | Replaces the 128-bit block that an immediate selects with four singles from a register or memory. | AVX10.1 |
| VINSERTF32X8 | Replaces the 256-bit block that an immediate selects with eight singles from a register or memory. | AVX10.1 |
| VINSERTF64X2 | Replaces the 128-bit block that an immediate selects with two doubles from a register or memory. | AVX10.1 |
| VINSERTF64X4 | Replaces the 256-bit block that an immediate selects with four doubles from a register or memory. | AVX10.1 |
| VINSERTI32X4 | Replaces the 128-bit block that an immediate selects with four doublewords from a register or memory. | AVX10.1 |
| VINSERTI32X8 | Replaces the 256-bit block that an immediate selects with eight doublewords from a register or memory. | AVX10.1 |
| VINSERTI64X2 | Replaces the 128-bit block that an immediate selects with two quadwords from a register or memory. | AVX10.1 |
| VINSERTI64X4 | Replaces the 256-bit block that an immediate selects with four quadwords from a register or memory. | AVX10.1 |
| VINSERTPS | Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements. | AVX10.1 |
| VMAXBF16 | Returns the larger of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMAXPD | Returns the larger of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMAXPH | Returns the larger of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMAXPS | Returns the larger of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMAXSD | Returns the larger of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMAXSH | Returns the larger low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMAXSS | Returns the larger of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMINBF16 | Returns the smaller of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMINMAXBF16 | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed bfloat16 values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINPD | Returns the smaller of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMINPH | Returns the smaller of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMINPS | Returns the smaller of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMINSD | Returns the smaller of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMINSH | Returns the smaller low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMINSS | Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMOVAPD | Moves packed doubles between registers and memory that must be aligned to the vector size. | AVX10.1 |
| VMOVAPS | Moves packed singles between registers and memory that must be aligned to the vector size. | AVX10.1 |
| VMOVD | Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX10.1, AVX10.2 |
| VMOVDDUP | Duplicates each even-numbered double into the next odd position. | AVX10.1 |
| VMOVDQA32 | Moves integer vectors between registers and aligned memory, masked at doubleword granularity. | AVX10.1 |
| VMOVDQA64 | Moves integer vectors between registers and aligned memory, masked at quadword granularity. | AVX10.1 |
| VMOVDQU16 | Moves integer vectors between registers and memory without an alignment requirement, masked at word granularity. | AVX10.1 |
| VMOVDQU32 | Moves integer vectors between registers and memory without an alignment requirement, masked at doubleword granularity. | AVX10.1 |
| VMOVDQU64 | Moves integer vectors between registers and memory without an alignment requirement, masked at quadword granularity. | AVX10.1 |
| VMOVDQU8 | Moves integer vectors between registers and memory without an alignment requirement, masked at byte granularity. | AVX10.1 |
| VMOVHLPS | Moves the high two singles of the second source into the low half of the result, the high half coming from the first source. | AVX10.1 |
| VMOVHPD | Loads a double from memory into the high half of an XMM register, or stores the high double to memory. | AVX10.1 |
| VMOVHPS | Loads two singles from memory into the high half of an XMM register, or stores the high two to memory. | AVX10.1 |
| VMOVLHPS | Moves the low two singles of the second source into the high half of the result, the low half coming from the first source. | AVX10.1 |
| VMOVLPD | Loads a double from memory into the low half of an XMM register, or stores the low double to memory. | AVX10.1 |
| VMOVLPS | Loads two singles from memory into the low half of an XMM register, or stores the low two to memory. | AVX10.1 |
| VMOVNTDQ | Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX10.1 |
| VMOVNTDQA | Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently. | AVX10.1 |
| VMOVNTPD | Stores packed doubles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX10.1 |
| VMOVNTPS | Stores packed singles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX10.1 |
| VMOVQ | Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination. | AVX10.1 |
| VMOVRSB | Loads a vector of bytes under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSD | Loads a vector of doublewords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSQ | Loads a vector of quadwords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSW | Loads a vector of words under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVSD | Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX10.1 |
| VMOVSH | Moves the low half-precision value between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX10.1 |
| VMOVSHDUP | Duplicates each odd-numbered single into the even position below it. | AVX10.1 |
| VMOVSLDUP | Duplicates each even-numbered single into the odd position above it. | AVX10.1 |
| VMOVSS | Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX10.1 |
| VMOVUPD | Moves packed doubles between registers and memory without an alignment requirement. | AVX10.1 |
| VMOVUPS | Moves packed singles between registers and memory without an alignment requirement. | AVX10.1 |
| VMOVW | Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX10.1, AVX10.2 |
| VMPSADBW | Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first. | AVX10.2 |
| VMULBF16 | Multiplies packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VMULPD | Multiplies packed doubles. | AVX10.1 |
| VMULPH | Multiplies packed half-precision values. | AVX10.1 |
| VMULPS | Multiplies packed singles. | AVX10.1 |
| VMULSD | Multiplies the low doubles; the other elements come from the first source. | AVX10.1 |
| VMULSH | Multiplies the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VMULSS | Multiplies the low singles; the other elements come from the first source. | AVX10.1 |
| VORPD | Computes the bitwise OR of packed doubles. | AVX10.1 |
| VORPS | Computes the bitwise OR of packed singles. | AVX10.1 |
| VPABSB | Computes the absolute value of packed signed bytes. | AVX10.1 |
| VPABSD | Computes the absolute value of packed signed doublewords. | AVX10.1 |
| VPABSQ | Computes the absolute value of packed signed quadwords. | AVX10.1 |
| VPABSW | Computes the absolute value of packed signed words. | AVX10.1 |
| VPACKSSDW | Narrows signed doublewords from two sources to words with signed saturation. | AVX10.1 |
| VPACKSSWB | Narrows signed words from two sources to bytes with signed saturation. | AVX10.1 |
| VPACKUSDW | Narrows signed doublewords from two sources to words with unsigned saturation. | AVX10.1 |
| VPACKUSWB | Narrows signed words from two sources to bytes with unsigned saturation. | AVX10.1 |
| VPADDB | Adds packed bytes, wrapping around on overflow. | AVX10.1 |
| VPADDD | Adds packed doublewords, wrapping around on overflow. | AVX10.1 |
| VPADDQ | Adds packed quadwords, wrapping around on overflow. | AVX10.1 |
| VPADDSB | Adds packed signed bytes with signed saturation. | AVX10.1 |
| VPADDSW | Adds packed signed words with signed saturation. | AVX10.1 |
| VPADDUSB | Adds packed unsigned bytes with unsigned saturation. | AVX10.1 |
| VPADDUSW | Adds packed unsigned words with unsigned saturation. | AVX10.1 |
| VPADDW | Adds packed words, wrapping around on overflow. | AVX10.1 |
| VPALIGNR | Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate. | AVX10.1 |
| VPANDD | Computes the bitwise AND of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPANDND | Computes the bitwise AND of the inverted first source with the second, masked at doubleword granularity. | AVX10.1 |
| VPANDNQ | Computes the bitwise AND of the inverted first source with the second, masked at quadword granularity. | AVX10.1 |
| VPANDQ | Computes the bitwise AND of two vectors, masked at quadword granularity. | AVX10.1 |
| VPAVGB | Computes the rounded average of packed unsigned bytes. | AVX10.1 |
| VPAVGW | Computes the rounded average of packed unsigned words. | AVX10.1 |
| VPBLENDMB | Picks each byte from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMD | Picks each doubleword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMQ | Picks each quadword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMW | Picks each word from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBROADCASTB | Copies one byte from a register or memory to every byte of a vector. | AVX10.1 |
| VPBROADCASTD | Copies one doubleword from a register or memory to every doubleword of a vector. | AVX10.1 |
| VPBROADCASTMB2Q | Copies the low 8 bits of a mask register, zero-extended, to every quadword. | AVX10.1 |
| VPBROADCASTMW2D | Copies the low 16 bits of a mask register, zero-extended, to every doubleword. | AVX10.1 |
| VPBROADCASTQ | Copies one quadword from a register or memory to every quadword of a vector. | AVX10.1 |
| VPBROADCASTW | Copies one word from a register or memory to every word of a vector. | AVX10.1 |
| VPCLMULQDQ | Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane. | AVX10.1 |
| VPCMPB | Compares packed signed bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPD | Compares packed signed doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPEQB | Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPEQD | Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPEQQ | Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPEQW | Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPGTB | Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPGTD | Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPGTQ | Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPGTW | Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX10.1 |
| VPCMPQ | Compares packed signed quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUB | Compares packed unsigned bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUD | Compares packed unsigned doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUQ | Compares packed unsigned quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUW | Compares packed unsigned words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPW | Compares packed signed words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCOMPRESSB | Packs the bytes selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSD | Packs the doublewords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSQ | Packs the quadwords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSW | Packs the words selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCONFLICTD | For each doubleword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPCONFLICTQ | For each quadword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPDPBSSD | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSSDS | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator with signed saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUD | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUDS | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUSD | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPBUSDS | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI, AVX10.1 |
| VPDPBUUD | Multiplies unsigned bytes by unsigned bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUUDS | Multiplies unsigned bytes by unsigned bytes and adds each group of four products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPWSSD | Multiplies pairs of signed words, adds both products to the matching 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPWSSDS | Multiplies pairs of signed words and adds both products to the matching 32-bit accumulator with signed saturation. | AVX-VNNI, AVX10.1 |
| VPDPWSUD | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWSUDS | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSD | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSDS | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUD | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUDS | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT16, AVX10.2 |
| VPERMB | Rearranges the bytes of a vector across the whole register using an index vector. | AVX10.1 |
| VPERMD | Rearranges the doublewords of a vector across the whole register using an index vector. | AVX10.1 |
| VPERMI2B | Selects bytes from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2D | Selects doublewords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PD | Selects doubles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PS | Selects singles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2Q | Selects quadwords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2W | Selects words from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMILPD | Rearranges doubles within each 128-bit lane, controlled by an immediate or by a vector. | AVX10.1 |
| VPERMILPS | Rearranges singles within each 128-bit lane, controlled by an immediate or by a vector. | AVX10.1 |
| VPERMPD | Rearranges doubles across the whole register, controlled by an immediate or by an index vector. | AVX10.1 |
| VPERMPS | Rearranges singles across the whole register using an index vector. | AVX10.1 |
| VPERMQ | Rearranges quadwords across the whole register, controlled by an immediate or by an index vector. | AVX10.1 |
| VPERMT2B | Selects bytes from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2D | Selects doublewords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PD | Selects doubles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PS | Selects singles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2Q | Selects quadwords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2W | Selects words from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMW | Rearranges the words of a vector across the whole register using an index vector. | AVX10.1 |
| VPEXPANDB | Spreads consecutive bytes from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDD | Spreads consecutive doublewords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDQ | Spreads consecutive quadwords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDW | Spreads consecutive words from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXTRB | Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory. | AVX10.1 |
| VPEXTRD | Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX10.1 |
| VPEXTRQ | Copies the quadword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX10.1 |
| VPEXTRW | Copies the word selected by an immediate from an XMM register to a general-purpose register or memory. | AVX10.1 |
| VPGATHERDD | Loads doublewords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPGATHERDQ | Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPGATHERQD | Loads doublewords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPGATHERQQ | Loads quadwords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPINSRB | Inserts a byte from a register or memory into an XMM register at the position an immediate gives. | AVX10.1 |
| VPINSRD | Inserts a doubleword from a register or memory into an XMM register at the position an immediate gives. | AVX10.1 |
| VPINSRQ | Inserts a quadword from a register or memory into an XMM register at the position an immediate gives. | AVX10.1 |
| VPINSRW | Inserts a word from a register or memory into an XMM register at the position an immediate gives. | AVX10.1 |
| VPLZCNTD | Counts the leading zero bits of each doubleword. | AVX10.1 |
| VPLZCNTQ | Counts the leading zero bits of each quadword. | AVX10.1 |
| VPMADD52HUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADD52LUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the low 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADDUBSW | Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation. | AVX10.1 |
| VPMADDWD | Multiplies signed words and adds adjacent products into doublewords. | AVX10.1 |
| VPMAXSB | Returns the larger of each pair of signed bytes. | AVX10.1 |
| VPMAXSD | Returns the larger of each pair of signed doublewords. | AVX10.1 |
| VPMAXSQ | Returns the larger of each pair of signed quadwords. | AVX10.1 |
| VPMAXSW | Returns the larger of each pair of signed words. | AVX10.1 |
| VPMAXUB | Returns the larger of each pair of unsigned bytes. | AVX10.1 |
| VPMAXUD | Returns the larger of each pair of unsigned doublewords. | AVX10.1 |
| VPMAXUQ | Returns the larger of each pair of unsigned quadwords. | AVX10.1 |
| VPMAXUW | Returns the larger of each pair of unsigned words. | AVX10.1 |
| VPMINSB | Returns the smaller of each pair of signed bytes. | AVX10.1 |
| VPMINSD | Returns the smaller of each pair of signed doublewords. | AVX10.1 |
| VPMINSQ | Returns the smaller of each pair of signed quadwords. | AVX10.1 |
| VPMINSW | Returns the smaller of each pair of signed words. | AVX10.1 |
| VPMINUB | Returns the smaller of each pair of unsigned bytes. | AVX10.1 |
| VPMINUD | Returns the smaller of each pair of unsigned doublewords. | AVX10.1 |
| VPMINUQ | Returns the smaller of each pair of unsigned quadwords. | AVX10.1 |
| VPMINUW | Returns the smaller of each pair of unsigned words. | AVX10.1 |
| VPMOVB2M | Sets each bit of a mask register from the sign bit of the corresponding byte. | AVX10.1 |
| VPMOVD2M | Sets each bit of a mask register from the sign bit of the corresponding doubleword. | AVX10.1 |
| VPMOVDB | Narrows packed doublewords to bytes by truncation. | AVX10.1 |
| VPMOVDW | Narrows packed doublewords to words by truncation. | AVX10.1 |
| VPMOVM2B | Sets each byte to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2D | Sets each doubleword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2Q | Sets each quadword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2W | Sets each word to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVQ2M | Sets each bit of a mask register from the sign bit of the corresponding quadword. | AVX10.1 |
| VPMOVQB | Narrows packed quadwords to bytes by truncation. | AVX10.1 |
| VPMOVQD | Narrows packed quadwords to doublewords by truncation. | AVX10.1 |
| VPMOVQW | Narrows packed quadwords to words by truncation. | AVX10.1 |
| VPMOVSDB | Narrows packed signed doublewords to bytes with signed saturation. | AVX10.1 |
| VPMOVSDW | Narrows packed signed doublewords to words with signed saturation. | AVX10.1 |
| VPMOVSQB | Narrows packed signed quadwords to bytes with signed saturation. | AVX10.1 |
| VPMOVSQD | Narrows packed signed quadwords to doublewords with signed saturation. | AVX10.1 |
| VPMOVSQW | Narrows packed signed quadwords to words with signed saturation. | AVX10.1 |
| VPMOVSSDB | Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127. | AVX10_V2_AUX |
| VPMOVSWB | Narrows packed signed words to bytes with signed saturation. | AVX10.1 |
| VPMOVSXBD | Sign-extends packed bytes to doublewords. | AVX10.1 |
| VPMOVSXBQ | Sign-extends packed bytes to quadwords. | AVX10.1 |
| VPMOVSXBW | Sign-extends packed bytes to words. | AVX10.1 |
| VPMOVSXDQ | Sign-extends packed doublewords to quadwords. | AVX10.1 |
| VPMOVSXWD | Sign-extends packed words to doublewords. | AVX10.1 |
| VPMOVSXWQ | Sign-extends packed words to quadwords. | AVX10.1 |
| VPMOVUSDB | Narrows packed unsigned doublewords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSDW | Narrows packed unsigned doublewords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSQB | Narrows packed unsigned quadwords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSQD | Narrows packed unsigned quadwords to doublewords with unsigned saturation. | AVX10.1 |
| VPMOVUSQW | Narrows packed unsigned quadwords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSWB | Narrows packed unsigned words to bytes with unsigned saturation. | AVX10.1 |
| VPMOVW2M | Sets each bit of a mask register from the sign bit of the corresponding word. | AVX10.1 |
| VPMOVWB | Narrows packed words to bytes by truncation. | AVX10.1 |
| VPMOVZXBD | Zero-extends packed bytes to doublewords. | AVX10.1 |
| VPMOVZXBQ | Zero-extends packed bytes to quadwords. | AVX10.1 |
| VPMOVZXBW | Zero-extends packed bytes to words. | AVX10.1 |
| VPMOVZXDQ | Zero-extends packed doublewords to quadwords. | AVX10.1 |
| VPMOVZXWD | Zero-extends packed words to doublewords. | AVX10.1 |
| VPMOVZXWQ | Zero-extends packed words to quadwords. | AVX10.1 |
| VPMULDQ | Multiplies the signed low doublewords of each quadword into 64-bit products. | AVX10.1 |
| VPMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result. | AVX10.1 |
| VPMULHUW | Multiplies unsigned words and keeps the high 16 bits of each product. | AVX10.1 |
| VPMULHW | Multiplies signed words and keeps the high 16 bits of each product. | AVX10.1 |
| VPMULLD | Multiplies packed doublewords and keeps the low 32 bits of each product. | AVX10.1 |
| VPMULLQ | Multiplies packed quadwords and keeps the low 64 bits of each product. | AVX10.1 |
| VPMULLW | Multiplies packed words and keeps the low 16 bits of each product. | AVX10.1 |
| VPMULTISHIFTQB | For each byte of the result, takes 8 bits from the matching quadword of the second source at a bit offset given by a control byte of the first. | AVX10.1 |
| VPMULUDQ | Multiplies the unsigned low doublewords of each quadword into 64-bit products. | AVX10.1 |
| VPOPCNTB | Counts the set bits in each byte. | AVX10.1 |
| VPOPCNTD | Counts the set bits in each doubleword. | AVX10.1 |
| VPOPCNTQ | Counts the set bits in each quadword. | AVX10.1 |
| VPOPCNTW | Counts the set bits in each word. | AVX10.1 |
| VPORD | Computes the bitwise OR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPORQ | Computes the bitwise OR of two vectors, masked at quadword granularity. | AVX10.1 |
| VPROLD | Rotates each doubleword left by an immediate count. | AVX10.1 |
| VPROLQ | Rotates each quadword left by an immediate count. | AVX10.1 |
| VPROLVD | Rotates each doubleword left by the count in the matching element of the second source. | AVX10.1 |
| VPROLVQ | Rotates each quadword left by the count in the matching element of the second source. | AVX10.1 |
| VPRORD | Rotates each doubleword right by an immediate count. | AVX10.1 |
| VPRORQ | Rotates each quadword right by an immediate count. | AVX10.1 |
| VPRORVD | Rotates each doubleword right by the count in the matching element of the second source. | AVX10.1 |
| VPRORVQ | Rotates each quadword right by the count in the matching element of the second source. | AVX10.1 |
| VPSADBW | Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword. | AVX10.1 |
| VPSCATTERDD | Stores doublewords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERDQ | Stores quadwords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQD | Stores doublewords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQQ | Stores quadwords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSHLDD | Joins each doubleword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDQ | Joins each quadword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDVD | Joins each doubleword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVQ | Joins each quadword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVW | Joins each word of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDW | Joins each word of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHRDD | Joins each doubleword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDQ | Joins each quadword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDVD | Joins each doubleword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVQ | Joins each quadword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVW | Joins each word of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDW | Joins each word of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHUFB | Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set. | AVX10.1 |
| VPSHUFBITQMB | Selects, for each byte of the second source, one bit of the matching quadword of the first and writes the bits to a mask register. | AVX10.1 |
| VPSHUFD | Rearranges doublewords within each 128-bit lane as an immediate selects. | AVX10.1 |
| VPSHUFHW | Rearranges the upper four words of each 128-bit lane as an immediate selects. | AVX10.1 |
| VPSHUFLW | Rearranges the lower four words of each 128-bit lane as an immediate selects. | AVX10.1 |
| VPSLLD | Shifts doublewords left by one count from a register or an immediate. | AVX10.1 |
| VPSLLDQ | Shifts each 128-bit lane left by a number of bytes given by an immediate. | AVX10.1 |
| VPSLLQ | Shifts quadwords left by one count from a register or an immediate. | AVX10.1 |
| VPSLLVD | Shifts each doubleword left by the count in the matching element of the second source. | AVX10.1 |
| VPSLLVQ | Shifts each quadword left by the count in the matching element of the second source. | AVX10.1 |
| VPSLLVW | Shifts each word left by the count in the matching element of the second source. | AVX10.1 |
| VPSLLW | Shifts words left by one count from a register or an immediate. | AVX10.1 |
| VPSRAD | Shifts doublewords right arithmetically by one count from a register or an immediate. | AVX10.1 |
| VPSRAQ | Shifts quadwords right arithmetically by one count from a register or an immediate. | AVX10.1 |
| VPSRAVD | Shifts each doubleword right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAVQ | Shifts each quadword right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAVW | Shifts each word right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAW | Shifts words right arithmetically by one count from a register or an immediate. | AVX10.1 |
| VPSRLD | Shifts doublewords right logically by one count from a register or an immediate. | AVX10.1 |
| VPSRLDQ | Shifts each 128-bit lane right by a number of bytes given by an immediate. | AVX10.1 |
| VPSRLQ | Shifts quadwords right logically by one count from a register or an immediate. | AVX10.1 |
| VPSRLVD | Shifts each doubleword right logically by the count in the matching element of the second source. | AVX10.1 |
| VPSRLVQ | Shifts each quadword right logically by the count in the matching element of the second source. | AVX10.1 |
| VPSRLVW | Shifts each word right logically by the count in the matching element of the second source. | AVX10.1 |
| VPSRLW | Shifts words right logically by one count from a register or an immediate. | AVX10.1 |
| VPSUBB | Subtracts packed bytes, wrapping around on overflow. | AVX10.1 |
| VPSUBD | Subtracts packed doublewords, wrapping around on overflow. | AVX10.1 |
| VPSUBQ | Subtracts packed quadwords, wrapping around on overflow. | AVX10.1 |
| VPSUBSB | Subtracts packed signed bytes with signed saturation. | AVX10.1 |
| VPSUBSW | Subtracts packed signed words with signed saturation. | AVX10.1 |
| VPSUBUSB | Subtracts packed unsigned bytes with unsigned saturation. | AVX10.1 |
| VPSUBUSW | Subtracts packed unsigned words with unsigned saturation. | AVX10.1 |
| VPSUBW | Subtracts packed words, wrapping around on overflow. | AVX10.1 |
| VPTERNLOGD | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at doubleword granularity. | AVX10.1 |
| VPTERNLOGQ | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at quadword granularity. | AVX10.1 |
| VPTESTMB | Sets a mask bit for each pair of bytes whose AND is not zero. | AVX10.1 |
| VPTESTMD | Sets a mask bit for each pair of doublewords whose AND is not zero. | AVX10.1 |
| VPTESTMQ | Sets a mask bit for each pair of quadwords whose AND is not zero. | AVX10.1 |
| VPTESTMW | Sets a mask bit for each pair of words whose AND is not zero. | AVX10.1 |
| VPTESTNMB | Sets a mask bit for each pair of bytes whose AND is zero. | AVX10.1 |
| VPTESTNMD | Sets a mask bit for each pair of doublewords whose AND is zero. | AVX10.1 |
| VPTESTNMQ | Sets a mask bit for each pair of quadwords whose AND is zero. | AVX10.1 |
| VPTESTNMW | Sets a mask bit for each pair of words whose AND is zero. | AVX10.1 |
| VPUNPCKHBW | Interleaves the high bytes of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKHDQ | Interleaves the high doublewords of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKHQDQ | Interleaves the high quadwords of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKHWD | Interleaves the high words of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKLBW | Interleaves the low bytes of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKLDQ | Interleaves the low doublewords of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKLQDQ | Interleaves the low quadwords of each 128-bit lane of two sources. | AVX10.1 |
| VPUNPCKLWD | Interleaves the low words of each 128-bit lane of two sources. | AVX10.1 |
| VPXORD | Computes the bitwise XOR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPXORQ | Computes the bitwise XOR of two vectors, masked at quadword granularity. | AVX10.1 |
| VRANGEPD | Computes the minimum, maximum, or value of smaller or larger magnitude of packed doubles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGEPS | Computes the minimum, maximum, or value of smaller or larger magnitude of packed singles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGESD | Computes the minimum, maximum, or smaller or larger magnitude of the low doubles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRANGESS | Computes the minimum, maximum, or smaller or larger magnitude of the low singles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRCP14PD | Approximates the reciprocal of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRCP14PS | Approximates the reciprocal of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRCP14SD | Approximates the reciprocal of the low double of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCP14SS | Approximates the reciprocal of the low single of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCPBF16 | Approximates the reciprocal of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRCPPH | Approximates the reciprocal of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRCPSH | Approximates the reciprocal of the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VREDUCEBF16 | Subtracts from each packed bfloat16 value its value rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.2 |
| VREDUCEPD | Subtracts from packed doubles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPH | Subtracts from packed half-precision values their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPS | Subtracts from packed singles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCESD | Subtracts from the low double of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VREDUCESH | Subtracts from the second source's low half-precision value that value rounded to an immediate's precision; the rest come from the first source. | AVX10.1 |
| VREDUCESS | Subtracts from the low single of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALEBF16 | Rounds each packed bfloat16 value to the number of fraction bits an immediate gives. | AVX10.2 |
| VRNDSCALEPD | Rounds packed doubles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPH | Rounds packed half-precision values to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPS | Rounds packed singles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALESD | Rounds the low double of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESH | Rounds the second source's low half-precision value to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESS | Rounds the low single of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRSQRT14PD | Approximates the reciprocal square root of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14PS | Approximates the reciprocal square root of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14SD | Approximates the reciprocal square root of the second source's low double, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRT14SS | Approximates the reciprocal square root of the second source's low single, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRTBF16 | Approximates the reciprocal square root of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRSQRTPH | Approximates the reciprocal square root of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRSQRTSH | Approximates 1/sqrt(x) for the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VSCALEFBF16 | Multiplies each packed bfloat16 value by 2 raised to the floor of the corresponding value of the second source. | AVX10.2 |
| VSCALEFPD | Multiplies packed doubles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPH | Multiplies packed half-precision values by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPS | Multiplies packed singles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFSD | Multiplies the low double by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCALEFSH | Multiplies the low half-precision value by 2 to the floor of the second source's low value; the other elements come from the first source. | AVX10.1 |
| VSCALEFSS | Multiplies the low single by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCATTERDPD | Stores doubles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERDPS | Stores singles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERQPD | Stores doubles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERQPS | Stores singles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSHA512MSG1 | Performs the first half of the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512MSG2 | Completes the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512RNDS2 | Performs two rounds of SHA-512 (and SHA-384) on the working state, using precomputed message and round-constant sums. | SHA512 |
| VSHUFF32X4 | Picks 128-bit blocks of singles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFF64X2 | Picks 128-bit blocks of doubles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI32X4 | Picks 128-bit blocks of doublewords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI64X2 | Picks 128-bit blocks of quadwords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFPD | Picks doubles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX10.1 |
| VSHUFPS | Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX10.1 |
| VSM3MSG1 | Performs the first part of the SM3 message expansion for the next four message words. | SM3 |
| VSM3MSG2 | Completes the SM3 message expansion for the next four message words. | SM3 |
| VSM3RNDS2 | Performs two rounds of the SM3 hash function, starting at the round number in an immediate. | SM3 |
| VSM4KEY4 | Performs four rounds of SM4 key expansion in each 128-bit lane. | SM4 |
| VSM4RNDS4 | Performs four rounds of SM4 encryption in each 128-bit lane. | SM4 |
| VSQRTBF16 | Computes the square root of each packed bfloat16 value, rounding to nearest, with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSQRTPD | Computes the square root of packed doubles. | AVX10.1 |
| VSQRTPH | Computes the square root of packed half-precision values. | AVX10.1 |
| VSQRTPS | Computes the square root of packed singles. | AVX10.1 |
| VSQRTSD | Computes the square root of the low double of the second source; the other elements come from the first source. | AVX10.1 |
| VSQRTSH | Computes the square root of the low half-precision value of the second source; the other elements come from the first source. | AVX10.1 |
| VSQRTSS | Computes the square root of the low single of the second source; the other elements come from the first source. | AVX10.1 |
| VSUBBF16 | Subtracts packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSUBPD | Subtracts packed doubles. | AVX10.1 |
| VSUBPH | Subtracts packed half-precision values. | AVX10.1 |
| VSUBPS | Subtracts packed singles. | AVX10.1 |
| VSUBSD | Subtracts the low doubles; the other elements come from the first source. | AVX10.1 |
| VSUBSH | Subtracts the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VSUBSS | Subtracts the low singles; the other elements come from the first source. | AVX10.1 |
| VUCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX10.1 |
| VUCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX10.1 |
| VUCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX10.1 |
| VUCOMXSD | Compares the low double-precision values of two operands like VCOMXSD but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSH | Compares the low half-precision values of two operands like VCOMXSH but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSS | Compares the low single-precision values of two operands like VCOMXSS but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUNPACKB | Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate. | AVX10_V2_AUX |
| VUNPCKHPD | Interleaves the high doubles of each 128-bit lane of two sources. | AVX10.1 |
| VUNPCKHPS | Interleaves the high singles of each 128-bit lane of two sources. | AVX10.1 |
| VUNPCKLPD | Interleaves the low doubles of each 128-bit lane of two sources. | AVX10.1 |
| VUNPCKLPS | Interleaves the low singles of each 128-bit lane of two sources. | AVX10.1 |
| VXORPD | Computes the bitwise XOR of packed doubles. | AVX10.1 |
| VXORPS | Computes the bitwise XOR of packed singles. | AVX10.1 |
| WRMSRLIST | Writes up to 64 model-specific registers from a table in memory to the addresses listed in a second table, selected by a bit mask in RCX. | MSRLIST |
| WRMSRNS | Writes a model-specific register like WRMSR but without serializing the processor; the MSR_IMM form takes the MSR number as an immediate. | WRMSRNS, MSR_IMM, APX |
| WRSSD | Writes a 32-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | APX |
| WRSSQ | Writes a 64-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | APX |
| WRUSSD | Lets ring-0 code write a 32-bit value to a user-mode shadow stack. | APX |
| WRUSSQ | Lets ring-0 code write a 64-bit value to a user-mode shadow stack. | APX |
| XADD | Exchanges a register with the destination and stores their sum in the destination; with LOCK it is the atomic fetch-and-add. | General-purpose |
| XCHG | Swaps two operands; with a memory operand it is atomic even without a LOCK prefix. | General-purpose |
| XLAT | Replaces AL with the byte at RBX plus AL, a table lookup; XLATB is the spelling without operands. | General-purpose |
| XOR | Computes the bitwise exclusive OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
Reading the tables
The tables follow the notation of Intel’s manuals, with a few additions for information that XED records.
Instruction
Operands are in Intel order, destination first.
r8,r16,r32,r64- General-purpose registers of that width.
r16/32/64means the operand size is chosen by the prefixes: 66 for 16 bits, REX.W (or EVEX.W) for 64 bits, 32 bits otherwise. m8tom512,m16/32/64- A memory operand of that many bits.
imm8,imm16/32,imm64- An immediate value encoded in the instruction.
rel8,rel32,rel16/32- A branch target as a signed offset from the next instruction.
m16:16/32/64,ptr16:16/32- A far pointer, a 16-bit segment selector and an offset of 16, 32 or 64 bits, in memory or as an immediate.
AL,eAX,rAX,DX- A fixed register.
eAXis AX or EAX andrAXAX, EAX or RAX, by operand size. sreg,cr,dr- A segment, control or debug register.
m- A memory operand of which only the address matters, as for LEA.
xmm,ymm,zmm,k,tmm- A 128-, 256- or 512-bit vector register, an AVX-512 mask register, or an AMX tile register.
{k},{k}{z}- The destination is written under a mask register; with
{z}, masked-off elements can be zeroed instead of kept. m512/m32bcst- Either a full vector in memory or one element that is broadcast to every position (EVEX.b set).
{er},{sae}- The register form accepts a rounding mode in the instruction (embedded rounding), or suppresses floating-point exceptions.
vm32x,vm64z- A vector of addresses for gathers and scatters: 32- or 64-bit indices in an xmm, ymm or zmm register (VSIB addressing).
sibmem- A memory operand that must be encoded with a SIB byte; AMX tile loads and stores use its index register as the row stride.
{dfv}- The flags that APX’s CCMP and CTEST set when their condition is false, encoded in the instruction.
cc,scc- A condition code. Mnemonics that differ only in their condition, such
as CMOVZ and CMOVNZ, share a page; the condition is part of the
opcode (
40+cc) or of the EVEX prefix (SC=scc). LOCK,REP- The form carries the prefix. XED lists these as separate instructions; here they appear on the page of the base mnemonic, as do the spellings of one instruction for each operand size, such as MOVSB to MOVSQ on the page of MOVS.
Encoding
66,F2,F3,NP- A prefix that is part of the opcode; NP means none of them is allowed.
67- The address-size prefix, for a form that uses a smaller address size than the mode’s default, such as JECXZ, which tests ECX, in 64-bit mode.
REX.W,REX2- A REX prefix with W set, or APX’s two-byte REX2 prefix (D5).
0F,0F 38,0F 3A- The escape bytes of the legacy opcode maps.
VEX.256.66.0F38.W0- A VEX or EVEX prefix with its fields: vector length (128, 256, 512;
LZorLLZmust be zero;LIGis ignored), implied prefix, opcode map (0F, 0F38, 0F3A, or MAP4 to MAP7) and the W bit (W0,W1,WIGfor ignored). SCALABLE- In APX forms of legacy instructions, EVEX.W selects 64-bit operands and the implied 66 prefix selects 16-bit ones, as REX.W and 66 do.
/r,/0to/7,C0- A ModR/M byte with a register operand in its reg field, with a fixed value in the reg field that extends the opcode, or a fixed ModR/M byte.
+r,+cc- A register number or a condition code added to the opcode byte.
ib,iw,id,io,/is4- An immediate of 1, 2, 4 or 8 bytes;
iw/iddepends on the operand size./is4is an immediate byte whose upper four bits name a register. ND=1,NF=1,NF=0/1- APX bits of the EVEX prefix: ND selects the new data destination, NF
suppresses the flag updates.
NF=0/1means the form exists both ways. (without BMI1)- The bytes mean this instruction only on processors without the named feature; on those with it, they are another instruction. F3 0F BC is BSF without BMI1 and TZCNT with it.
Tags
- NDD
- APX new data destination: the result goes to a separate register and the other operands are only read.
- NF
- APX “no flags”: the instruction leaves the arithmetic flags unchanged.
- ZU
- APX “zero upper”: the destination register is written in full, with zeros above the result.
- 64-bit mode only, not in 64-bit mode
- Where the form can be used. APX forms are always 64-bit only.
Requires
Each form belongs to an ISA set of XED. The column names the CPUID features that enable it; when there are alternatives, any one of them is enough. AVX-512 forms, for example, need either their AVX-512 feature bits or AVX10.1. Each page lists the exact CPUID bits and the processors that XED’s chip model gives each ISA set.