x86 instruction reference
x86 instructions from the general-purpose base to the newest extensions, with the syntax, encoding, CPUID requirement and processors of every form.
The reference covers the extensions listed under ISA extensions: the general-purpose and system instructions and the smaller sets around them, such as CMOV, BMI1, XSAVE, CET and SYSCALL; x87 and MMX; SSE to SSE4.2, AVX and AVX2, AVX10.1 and AVX10.2 and the VEX extensions around them; the AMX family and ACE; APX; the virtualization and security extensions VMX, TDX, SMX and SGX; system instructions such as FRED and the new MSR instructions; the Xeon Phi extensions; AMD’s own, from 3DNow!, SSE4a, XOP, FMA4 and TBM to SVM and SEV-SNP; and VIA’s PadLock. Together they cover every instruction that Intel XED decodes, and every mnemonic has a page that lists all of its forms. An instruction that performs one of several operations, chosen by the value of a register, lists these leaf functions, and each has a page of its own, such as GETSEC[SENTER] and ECREATE, the ENCLS leaf that starts an SGX enclave; in the table below, the leaf functions follow their instruction.
Syntax, encodings, CPUID bits and processor lists are generated from Intel XED, the encoder and decoder library that Intel publishes under the Apache License 2.0. The summary sentences and longer explanations are our own. Where Intel’s manuals describe an instruction, its page links to the page of the manual where the description starts, under Sources.
Instruction pages also list the C intrinsics that compile to the instruction, with the exact form each one compiles to, taken from Clang’s headers and checked by compiling every intrinsic. The x86 intrinsics A–Z index lists all of them.
Most vector instructions raise exceptions such as #UD, #GP and #PF by rules that they share with many other instructions, which Intel’s manuals call exception classes and XED records for every form. The exception classes explain each class in our own words, by processor mode, and list the instructions in it.
All of this data can be downloaded as insn.json (4.9 MB); the about page describes its format and licenses.
| Mnemonic | Summary | Extensions |
|---|---|---|
| AAA | Corrects AL after adding two unpacked BCD digits: if the low digit exceeds 9 or AF is set, adds 6 to AL and 1 to AH and sets CF and AF; not in 64-bit mode. | General-purpose |
| AAD | Turns the unpacked BCD digits in AH and AL into the binary number AL plus AH times the immediate base (10 as assembled) before a DIV; not in 64-bit mode. | General-purpose |
| AADD | Atomically adds a register to a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAM | Splits AL into two unpacked BCD digits after a MUL: AH gets AL divided by the immediate base (10 as assembled), AL the remainder; not in 64-bit mode. | General-purpose |
| AAND | Atomically ANDs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| AAS | Corrects AL after subtracting two unpacked BCD digits: if the low digit exceeds 9 or AF is set, subtracts 6 from AX and 1 from AH; not in 64-bit mode. | General-purpose |
| ADC | Adds two integers and the carry flag, the step that chains multi-word additions; APX adds a three-operand form. | General-purpose, APX |
| ADCX | Adds two unsigned integers and the carry flag and changes only CF, so a carry chain can run next to an ADOX chain; APX adds a three-operand form. | ADX, APX |
| ADD | Adds two integers and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ADDPD | Adds two packed doubles of the source to those of the destination XMM register. | SSE2 |
| ADDPS | Adds four packed singles of the source to those of the destination XMM register. | SSE |
| ADDSD | Adds the low double of the source to the low double of the destination; the upper half of the destination is kept. | SSE2 |
| ADDSS | Adds the low single of the source to the low single of the destination; the upper three elements are kept. | SSE |
| ADDSUBPD | Subtracts in the low double and adds in the high double, the step of complex multiplication; SSE3. | SSE3 |
| ADDSUBPS | Subtracts in the even-numbered singles and adds in the odd-numbered ones, the step of complex multiplication; SSE3. | SSE3 |
| ADOX | Adds two unsigned integers and the overflow flag and changes only OF, so a carry chain can run next to an ADCX chain; APX adds a three-operand form. | ADX, APX |
| AESDEC | Performs one round of AES decryption on the block in an XMM register with the round key of the source. | AES-NI |
| AESDEC128KL | Decrypts the block in an XMM register with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESDEC256KL | Decrypts the block in an XMM register with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESDECLAST | Performs the last round of AES decryption, without InvMixColumns, on a block with the round key of the source. | AES-NI |
| AESDECWIDE128KL | Decrypts eight blocks in XMM0 to XMM7 with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESDECWIDE256KL | Decrypts eight blocks in XMM0 to XMM7 with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESENC | Performs one round of AES encryption on the block in an XMM register with the round key of the source. | AES-NI |
| AESENC128KL | Encrypts the block in an XMM register with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESENC256KL | Encrypts the block in an XMM register with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 reports a bad handle. | Key Locker |
| AESENCLAST | Performs the last round of AES encryption, without MixColumns, on a block with the round key of the source. | AES-NI |
| AESENCWIDE128KL | Encrypts eight blocks in XMM0 to XMM7 with ten AES rounds, using the 128-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESENCWIDE256KL | Encrypts eight blocks in XMM0 to XMM7 with 14 AES rounds, using the 256-bit key of a Key Locker handle in memory; ZF=1 if the handle fails. | Key Locker |
| AESIMC | Applies InvMixColumns to an AES round key, turning encryption round keys into those of the equivalent decryption. | AES-NI |
| AESKEYGENASSIST | Computes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs. | AES-NI |
| AND | Computes the bitwise AND of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ANDN | Computes the bitwise AND of the inverted first source with the second source into a separate destination; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| ANDNPD | Computes the bitwise AND of the inverted destination with the source, as packed doubles. | SSE2 |
| ANDNPS | Computes the bitwise AND of the inverted destination with the source, as packed singles. | SSE |
| ANDPD | Computes the bitwise AND of two XMM operands, as packed doubles. | SSE2 |
| ANDPS | Computes the bitwise AND of two XMM operands, as packed singles. | SSE |
| AOR | Atomically ORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| ARPL | Raises the requested privilege level of a segment selector to that of another, setting ZF if it changed; not in 64-bit mode, where 63 is MOVSXD. | System |
| AXOR | Atomically XORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation. | RAO-INT, APX |
| BEXTR | Extracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged. | BMI1, APX, TBM |
| BLCFILL | Clears the bits below the lowest clear bit of a general-purpose register or memory (x & (x + 1)); TBM. | TBM |
| BLCI | Sets every bit but the lowest clear bit of the source (x | ~(x + 1)); TBM. | TBM |
| BLCIC | Isolates the lowest clear bit of the source as the only set bit (~x & (x + 1)); TBM. | TBM |
| BLCMSK | Makes a mask of the lowest clear bit of the source and the bits below it (x ^ (x + 1)); TBM. | TBM |
| BLCS | Sets the lowest clear bit of the source (x | (x + 1)); TBM. | TBM |
| BLENDPD | Picks each double from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| BLENDPS | Picks each single from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| BLENDVPD | Picks each double from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1. | SSE4.1 |
| BLENDVPS | Picks each single from the destination or the source by the sign bit of the matching element of XMM0; SSE4.1. | SSE4.1 |
| BLSFILL | Sets the bits below the lowest set bit of the source (x | (x - 1)); TBM. | TBM |
| BLSI | Isolates the lowest set bit of the source, clearing all others; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSIC | Clears the lowest set bit of the source and sets every other bit (~x | (x - 1)); TBM. | TBM |
| BLSMSK | Sets all bits up to and including the lowest set bit of the source and clears the rest; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BLSR | Clears the lowest set bit of the source; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| BNDCL | Raises a bound-range exception (#BR) if an address is below the lower bound in an MPX bound register; MPX has been removed. | MPX |
| BNDCN | Raises #BR if an address is above the upper bound of an MPX bound register, taken as stored rather than complemented as BNDCU does; MPX has been removed. | MPX |
| BNDCU | Raises #BR if an address is above the upper bound of an MPX bound register, which keeps it in one's complement; MPX has been removed. | MPX |
| BNDLDX | Loads the MPX bounds of a pointer from the bound tables in memory, found by the address the pointer is stored at; MPX has been removed. | MPX |
| BNDMK | Makes MPX bounds from a memory operand: the lower bound from its base, the upper from its address; MPX has been removed. | MPX |
| BNDMOV | Copies MPX bounds between bound registers, or between a bound register and memory; MPX has been removed. | MPX |
| BNDSTX | Stores the MPX bounds of a pointer into the bound tables in memory, found by the address the pointer is stored at; MPX has been removed. | MPX |
| BOUND | Raises a bound-range exception (#BR) unless a signed array index in a register lies within the two bounds stored in memory; not in 64-bit mode. | General-purpose |
| BSF | Writes the index of the lowest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSR | Writes the index of the highest set bit of the source to the destination; a zero source sets ZF and leaves the destination unchanged. | General-purpose |
| BSRINIT | ACE instruction that sets every byte of the block scale register to 7FH, the E8M0 encoding of a scale factor of 1.0. | ACE |
| BSRMOVF | ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half. | ACE |
| BSRMOVH | ACE instruction that moves the upper 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSRMOVL | ACE instruction that moves the lower 512 bits of the block scale register to or from a ZMM register or memory. | ACE |
| BSWAP | Reverses the byte order of a 32- or 64-bit register, converting between little- and big-endian values; with a 16-bit register the result is undefined. | General-purpose |
| BT | Copies the bit that a register or immediate offset selects in a register or memory operand into CF; a register offset can reach beyond a memory operand. | General-purpose |
| BTC | Copies the selected bit of a register or memory operand into CF and then inverts it; with LOCK the memory form is atomic. | General-purpose |
| BTR | Copies the selected bit of a register or memory operand into CF and then clears it; with LOCK the memory form is atomic. | General-purpose |
| BTS | Copies the selected bit of a register or memory operand into CF and then sets it; with LOCK the memory form is an atomic test-and-set. | General-purpose |
| BZHI | Clears the bits of the source from a given bit position upward; APX adds a form that leaves the flags unchanged. | BMI2, APX |
| CALL | Pushes the return address and jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| CBW | Sign-extends AL into AX, copying bit 7 of AL into every bit of AH (AT&T cbtw). | General-purpose |
| CCMPscc | APX conditional compare: if the flags meet a condition, compares two operands, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CDQ | Sign-extends EAX into EDX:EAX, filling EDX with the sign bit of EAX, typically before a 32-bit IDIV (AT&T cltd). | General-purpose |
| CDQE | Sign-extends EAX into RAX in 64-bit mode; compilers emit it, as cltq in AT&T syntax, to widen a signed 32-bit value. | General-purpose |
| CFCMOVcc | APX conditionally faulting move: on a false condition, memory is untouched and cannot fault; a register destination gets zero, or a source with NDD. | APX |
| CLAC | Clears the alignment-check flag (AC), so that SMAP again stops the kernel from touching user pages; ring 0 only. | SMAP |
| CLC | Clears the carry flag (CF). | General-purpose |
| CLD | Clears the direction flag (DF), so that string instructions step upward through memory; the System V and Microsoft ABIs require it clear at calls. | General-purpose |
| CLDEMOTE | Hints that the cache line holding a byte of memory should move from the core's caches to a more distant level, where other cores reach it sooner. | CLDEMOTE |
| CLFLUSH | Writes back and invalidates the cache line holding a byte of memory in every cache of the coherence domain, ordered with writes and other CLFLUSHes. | CLFLUSH |
| CLFLUSHOPT | Writes back and invalidates the cache line holding a byte of memory like CLFLUSH, but unordered with flushes of other lines, so several can overlap. | CLFLUSHOPT |
| CLGI | Clears the global interrupt flag (GIF), which holds off all external interrupts; AMD SVM. | SVM |
| CLI | Clears the interrupt flag (IF) to hold off maskable interrupts; where CPL is above IOPL it faults or clears the virtual interrupt flag instead. | General-purpose |
| CLRSSBSY | Clears the busy flag of a supervisor shadow-stack token in memory and zeroes the shadow-stack pointer; not with FRED. | CET |
| CLTS | Clears the task-switched flag (TS) in CR0, which trapped the first x87 or SSE use after a task switch; ring 0 only. | System |
| CLUI | Clears the user interrupt flag (UIF), holding user interrupts back from the next instruction on. | UINTR |
| CLWB | Writes the cache line holding a byte of memory back if it was modified and may keep it cached, for example to make stores to persistent memory durable. | CLWB |
| CLZERO | Writes zeros to the whole cache line that contains the address in rAX. | CLZERO |
| CMC | Inverts the carry flag (CF). | General-purpose |
| CMOVcc | Copies the source to a register if a condition on the flags holds; APX adds a three-operand form that picks one of two sources. | CMOV, APX |
| CMP | Compares two operands by subtracting the second from the first, setting the arithmetic flags as SUB would and discarding the result. | General-purpose |
| CMPccXADD | Atomically compares memory with a register, adds a second register to memory if the condition holds, and returns the old value in the first. | CMPccXADD, APX |
| CMPPD | Compares two packed doubles with one of eight predicates an immediate selects, into all-ones or all-zeros elements. | SSE2 |
| CMPPS | Compares four packed singles with one of eight predicates an immediate selects, into all-ones or all-zeros elements. | SSE |
| CMPS | Compares the element at [RSI] with the one at [RDI], setting the flags as CMP would, and steps both pointers; REPE and REPNE repeat it. | General-purpose |
| CMPSD | Compares the low doubles with one of eight predicates an immediate selects, into an all-ones or all-zeros element. | SSE2 |
| CMPSS | Compares the low singles with one of eight predicates an immediate selects, into an all-ones or all-zeros element. | SSE |
| CMPXCHG | Compares the accumulator with the destination: if equal, stores the source there and sets ZF, else loads the destination; atomic with LOCK. | General-purpose |
| CMPXCHG16B | Compares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK. | CMPXCHG16B |
| CMPXCHG8B | Compares EDX:EAX with 8 bytes of memory: if equal, stores ECX:EBX there and sets ZF, else loads them into EDX:EAX; atomic with LOCK. | General-purpose |
| COMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception. | SSE2 |
| COMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN raises an invalid exception. | SSE |
| CPUID | Returns identification and feature information about the processor in EAX, EBX, ECX and EDX, for the leaf in EAX and the sub-leaf in ECX. | General-purpose |
| CQO | Sign-extends RAX into RDX:RAX, filling RDX with the sign bit of RAX, typically before a 64-bit IDIV (AT&T cqto); 64-bit mode only. | General-purpose |
| CRC32 | Accumulates a CRC-32C checksum (Castagnoli polynomial) over a 1-, 2-, 4- or 8-byte operand. | SSE4.2, APX |
| CTESTscc | APX conditional test: if the flags meet a condition, tests two operands with AND, otherwise sets OF, SF, ZF and CF to a value in the instruction. | APX |
| CVTDQ2PD | Converts the two low signed doublewords of the source to doubles. | SSE2 |
| CVTDQ2PS | Converts four packed signed doublewords to singles, rounding as MXCSR says. | SSE2 |
| CVTPD2DQ | Converts two packed doubles to signed doublewords in the low half, rounding as MXCSR says and zeroing the high half. | SSE2 |
| CVTPD2PI | Converts two packed doubles to signed doublewords in an MMX register, rounding as MXCSR says. | SSE2 |
| CVTPD2PS | Converts two packed doubles to singles in the low half, rounding as MXCSR says and zeroing the high half. | SSE2 |
| CVTPI2PD | Converts two signed doublewords from an MMX register or memory to doubles. | SSE2 |
| CVTPI2PS | Converts two signed doublewords from an MMX register or memory to the low two singles of an XMM register. | SSE |
| CVTPS2DQ | Converts four packed singles to signed doublewords, rounding as MXCSR says. | SSE2 |
| CVTPS2PD | Converts the two low singles of the source to doubles, which is exact. | SSE2 |
| CVTPS2PI | Converts the two low singles to signed doublewords in an MMX register, rounding as MXCSR says. | SSE |
| CVTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says. | SSE2 |
| CVTSD2SS | Converts the low double of the source to single, rounding as MXCSR says; the other elements of the destination are kept. | SSE2 |
| CVTSI2SD | Converts a signed 32- or 64-bit integer to double in the low element; the upper half of the destination is kept. | SSE2 |
| CVTSI2SS | Converts a signed 32- or 64-bit integer to single in the low element; the other elements of the destination are kept. | SSE |
| CVTSS2SD | Converts the low single of the source to double, which is exact; the upper half of the destination is kept. | SSE2 |
| CVTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says. | SSE |
| CVTTPD2DQ | Converts two packed doubles to signed doublewords in the low half, truncating toward zero and zeroing the high half. | SSE2 |
| CVTTPD2PI | Converts two packed doubles to signed doublewords in an MMX register, truncating toward zero. | SSE2 |
| CVTTPS2DQ | Converts four packed singles to signed doublewords, truncating toward zero. | SSE2 |
| CVTTPS2PI | Converts the two low singles to signed doublewords in an MMX register, truncating toward zero. | SSE |
| CVTTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | SSE2 |
| CVTTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | SSE |
| CWD | Sign-extends AX into DX:AX, filling DX with the sign bit of AX, typically before a 16-bit IDIV (AT&T cwtd). | General-purpose |
| CWDE | Sign-extends AX into EAX (AT&T cwtl); in 64-bit mode the write to EAX also clears the upper half of RAX. | General-purpose |
| DAA | Corrects AL after adding two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal carry; not in 64-bit mode. | General-purpose |
| DAS | Corrects AL after subtracting two packed BCD numbers so that it holds two decimal digits, setting CF on a decimal borrow; not in 64-bit mode. | General-purpose |
| DEC | Subtracts one from an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| DIV | Divides an unsigned double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| DIVPD | Divides the two packed doubles of the destination XMM register by those of the source. | SSE2 |
| DIVPS | Divides the four packed singles of the destination XMM register by those of the source. | SSE |
| DIVSD | Divides the low double of the destination by the low double of the source; the upper half is kept. | SSE2 |
| DIVSS | Divides the low single of the destination by the low single of the source; the upper three elements are kept. | SSE |
| DPPD | Computes a dot product of the packed doubles, with an immediate choosing which products to add and where the sum goes; SSE4.1. | SSE4.1 |
| DPPS | Computes a dot product of the packed singles, with an immediate choosing which products to add and where the sum goes; SSE4.1. | SSE4.1 |
| EMMS | Marks every x87 register empty at the end of MMX code, so that x87 instructions can use the register stack again. | MMX |
| ENCLS | Performs the SGX leaf function for the operating system that EAX selects, such as ECREATE or EADD; only CPL 0 may run it. | SGX |
| ECREATE | Starts building an enclave by copying its control structure, the SECS, from ordinary memory into a page of the EPC. | SGX |
| EADD | Copies a page from ordinary memory into the EPC for an enclave being built, and adds its offset and attributes to the enclave's measurement. | SGX |
| EINIT | Completes the build of an enclave: checks its signed SIGSTRUCT and launch token, fixes its measurement and makes it ready for EENTER. | SGX |
| EREMOVE | Removes a page from the EPC, detaching it from its enclave and marking it unused. | SGX |
| EDBGRD | Reads eight bytes (four outside 64-bit mode) of a debug enclave's memory, at the address in RCX, into RBX. | SGX |
| EDBGWR | Writes RBX (EBX outside 64-bit mode) to a debug enclave's memory at the address in RCX. | SGX |
| EEXTEND | Adds 256 bytes of a page of an enclave being built to the enclave's measurement, MRENCLAVE. | SGX |
| ELDB | Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and marks it blocked. | SGX |
| ELDU | Loads a page that EWB wrote out back into the EPC, checking and decrypting it, and leaves it unblocked. | SGX |
| EBLOCK | Marks an EPC page as blocked, the first step of evicting it from the EPC. | SGX |
| EPA | Turns an EPC page into a version array, which holds the versions of pages evicted from the EPC. | SGX |
| EWB | Evicts a blocked EPC page: encrypts it, writes it to ordinary memory and keeps its version in a version array. | SGX |
| ETRACK | Starts tracking the TLB flushes that must follow EBLOCK before the blocked pages of an enclave can be evicted. | SGX |
| EAUG | Adds a zeroed page to an enclave that is already running; the enclave must accept it with EACCEPT or EACCEPTCOPY. | SGX |
| EMODPR | Restricts the access rights of a page of a running enclave, which then accepts the change with EACCEPT. | SGX |
| EMODT | Changes the type of a page of a running enclave, to trim it for example, which then accepts the change with EACCEPT. | SGX |
| EUPDATESVN | Updates the SGX security version of the processor to that of the loaded microcode update, when the EPC holds no valid page. | SGX |
| ENCLU | Performs the SGX leaf function for applications and enclaves that EAX selects, such as EENTER or EGETKEY; only CPL 3 may run it. | SGX |
| EREPORT | Creates a report of the running enclave that a target enclave on the same platform can verify, for local attestation. | SGX |
| EGETKEY | Returns a 128-bit key from the processor's key hierarchy, such as a sealing key, as a KEYREQUEST structure asks. | SGX |
| EENTER | Enters an enclave through one of its thread control structures (TCS), at the entry point that the TCS gives. | SGX |
| ERESUME | Re-enters an enclave that an exception or interrupt left, with the state saved in its SSA frame. | SGX |
| EEXIT | Leaves the running enclave and continues at the address in RBX, outside it. | SGX |
| EACCEPT | Lets a running enclave accept a change that system software made to one of its pages with EAUG, EMODT or EMODPR. | SGX |
| EMODPE | Extends the access rights of a page of the running enclave, which the enclave may do by itself. | SGX |
| EACCEPTCOPY | Initializes a page that EAUG added by copying another page of the enclave into it, and accepts it. | SGX |
| EVERIFYREPORT2 | Checks, inside an enclave, the MAC of a report that a TDX trust domain created with SEAMREPORT. | SGX |
| EDECCSSA | Decrements the index of the current SSA frame (TCS.CSSA) of the enclave thread, from inside the enclave. | SGX |
| ENCLV | Performs the SGX virtualization leaf function that EAX selects; XED decodes it, but Intel's manual of September 2026 no longer documents it. | SGX |
| ENCODEKEY128 | Wraps the 128-bit AES key in XMM0 into a Key Locker handle in XMM0 to XMM2, so that software can discard the key itself. | Key Locker |
| ENCODEKEY256 | Wraps the 256-bit AES key in XMM0 and XMM1 into a Key Locker handle in XMM0 to XMM3, so that software can discard the key itself. | Key Locker |
| ENDBR32 | Marks a valid target of an indirect call or jump in 32-bit code for CET indirect branch tracking; a NOP on other processors. | CET |
| ENDBR64 | Marks a valid target of an indirect call or jump in 64-bit code for CET indirect branch tracking; a NOP on other processors. | CET |
| ENQCMD | Sends a 64-byte command, tagged with the PASID from the IA32_PASID MSR, to a device's enqueue register and sets ZF if the device did not accept it. | ENQCMD, APX |
| ENQCMDS | Kernel version of ENQCMD that takes the PASID and privilege bit of the 64-byte command from its memory operand instead of the IA32_PASID MSR. | ENQCMD, APX |
| ENTER | Makes a stack frame: pushes the frame pointer, copies outer frame pointers for nested procedures, and reserves the given bytes of locals. | General-purpose |
| ERETS | Returns from a FRED event handler to code that also runs in ring 0, restoring the interrupted context from the stack. | FRED |
| ERETU | Returns from a FRED event handler in ring 0 to ring 3, restoring the user context from the stack and swapping the GS base with IA32_KERNEL_GS_BASE. | FRED |
| EXTRACTPS | Copies the single that an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| EXTRQ | Extracts a bit field, whose length and position an immediate or a register gives, from the low quadword of an XMM register; SSE4a. | SSE4a |
| F2XM1 | Replaces ST(0), which must lie between -1 and +1, with 2 to the power ST(0), minus 1. | x87 |
| FABS | Clears the sign bit of ST(0), leaving its absolute value. | x87 |
| FADD | Adds a 32- or 64-bit float from memory to ST(0), or adds ST(0) and ST(i) into either of them. | x87 |
| FADDP | Adds ST(0) to ST(i), stores the sum in ST(i) and pops the register stack. | x87 |
| FBLD | Converts an 18-digit packed BCD integer from 10 bytes of memory to extended precision and pushes it. | x87 |
| FBSTP | Rounds ST(0) to an integer, stores it as 18-digit packed BCD in 10 bytes of memory and pops the register stack. | x87 |
| FCHS | Inverts the sign bit of ST(0). | x87 |
| FCMOVB | Copies ST(i) to ST(0) if CF is set (below, after FCOMI or an integer compare). | x87 |
| FCMOVBE | Copies ST(i) to ST(0) if CF or ZF is set (below or equal). | x87 |
| FCMOVE | Copies ST(i) to ST(0) if ZF is set (equal). | x87 |
| FCMOVNB | Copies ST(i) to ST(0) if CF is clear (not below). | x87 |
| FCMOVNBE | Copies ST(i) to ST(0) if both CF and ZF are clear (above). | x87 |
| FCMOVNE | Copies ST(i) to ST(0) if ZF is clear (not equal). | x87 |
| FCMOVNU | Copies ST(i) to ST(0) if PF is clear, which after FCOMI means the operands were ordered (neither was a NaN). | x87 |
| FCMOVU | Copies ST(i) to ST(0) if PF is set, which after FCOMI means the comparison was unordered (a NaN). | x87 |
| FCOM | Compares ST(0) with ST(i) or a 32- or 64-bit float in memory and sets C0, C2 and C3 of the x87 status word; any NaN is an invalid operation. | x87 |
| FCOMI | Compares ST(0) with ST(i) and sets ZF, PF and CF in EFLAGS directly; any NaN is an invalid operation. | x87 |
| FCOMIP | Compares ST(0) with ST(i) like FCOMI, setting ZF, PF and CF, then pops the register stack. | x87 |
| FCOMP | Compares ST(0) with ST(i) or a float in memory like FCOM, then pops the register stack. | x87 |
| FCOMPP | Compares ST(0) with ST(1) like FCOM, then pops the register stack twice. | x87 |
| FCOS | Replaces ST(0), an angle in radians of magnitude below 2^63, with its cosine; C2 reports an operand out of range. | x87 |
| FDECSTP | Subtracts one from the TOP field of the x87 status word, rotating the register stack without moving any data. | x87 |
| FDIV | Divides ST(0) by a float from memory, or ST(0) by ST(i) or ST(i) by ST(0), into the dividend's register. | x87 |
| FDIVP | Divides ST(i) by ST(0), stores the quotient in ST(i) and pops the register stack. | x87 |
| FDIVR | Divides a float from memory by ST(0), or ST(i) by ST(0) into ST(0), or ST(0) by ST(i) into ST(i): FDIV with the operands swapped. | x87 |
| FDIVRP | Divides ST(0) by ST(i), stores the quotient in ST(i) and pops the register stack. | x87 |
| FEMMS | Marks every x87 register empty at the end of 3DNow! or MMX code, exactly as EMMS does; AMD keeps it for older software. | 3DNow! |
| FFREE | Marks ST(i) as empty in the x87 tag word, without changing the stack top. | x87 |
| FFREEP | Marks ST(i) as empty and pops the register stack; Intel's manual does not list it, but XED decodes it. | x87 |
| FIADD | Adds a 16- or 32-bit signed integer from memory to ST(0). | x87 |
| FICOM | Compares ST(0) with a 16- or 32-bit signed integer in memory and sets C0, C2 and C3 of the x87 status word. | x87 |
| FICOMP | Compares ST(0) with a 16- or 32-bit signed integer in memory like FICOM, then pops the register stack. | x87 |
| FIDIV | Divides ST(0) by a 16- or 32-bit signed integer from memory. | x87 |
| FIDIVR | Divides a 16- or 32-bit signed integer from memory by ST(0), into ST(0). | x87 |
| FILD | Converts a 16-, 32- or 64-bit signed integer from memory to extended precision and pushes it. | x87 |
| FIMUL | Multiplies ST(0) by a 16- or 32-bit signed integer from memory. | x87 |
| FINCSTP | Adds one to the TOP field of the x87 status word, rotating the register stack without freeing a register. | x87 |
| FIST | Converts ST(0) to a 16- or 32-bit signed integer, rounded as the control word says, and stores it in memory. | x87 |
| FISTP | Converts ST(0) to a 16-, 32- or 64-bit signed integer as the rounding control says, stores it and pops the register stack. | x87 |
| FISTTP | Stores ST0 as a signed 16-, 32- or 64-bit integer, truncating toward zero whatever the rounding mode, and pops it; SSE3. | SSE3 |
| FISUB | Subtracts a 16- or 32-bit signed integer in memory from ST(0). | x87 |
| FISUBR | Subtracts ST(0) from a 16- or 32-bit signed integer in memory, into ST(0). | x87 |
| FLD | Pushes a 32-, 64- or 80-bit float from memory, or a copy of ST(i), onto the x87 register stack. | x87 |
| FLD1 | Pushes the constant +1.0 onto the x87 register stack. | x87 |
| FLDCW | Loads the x87 control word (exception masks, precision and rounding control) from 16 bits of memory. | x87 |
| FLDENV | Loads the x87 environment (control, status and tag words and the last instruction and operand pointers) from memory. | x87 |
| FLDL2E | Pushes the constant log2(e) onto the x87 register stack. | x87 |
| FLDL2T | Pushes the constant log2(10) onto the x87 register stack. | x87 |
| FLDLG2 | Pushes the constant log10(2) onto the x87 register stack. | x87 |
| FLDLN2 | Pushes the constant ln(2) onto the x87 register stack. | x87 |
| FLDPI | Pushes the constant pi onto the x87 register stack. | x87 |
| FLDZ | Pushes the constant +0.0 onto the x87 register stack. | x87 |
| FMUL | Multiplies ST(0) by a float from memory, or ST(0) and ST(i) into either of them. | x87 |
| FMULP | Multiplies ST(i) by ST(0), stores the product in ST(i) and pops the register stack. | x87 |
| FNCLEX | Clears the x87 exception flags without first handling pending exceptions; FCLEX is FWAIT followed by it. | x87 |
| FNDISI | An 8087 instruction that masked the coprocessor's interrupt; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNENI | An 8087 instruction that unmasked the coprocessor's interrupt; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNINIT | Resets the x87 unit to its default state without first handling pending exceptions; FINIT is FWAIT followed by it. | x87 |
| FNOP | Does nothing apart from updating the x87 instruction pointer. | x87 |
| FNSAVE | Stores the x87 environment and the eight data registers to memory, then resets the unit like FNINIT; FSAVE is FWAIT followed by it. | x87 |
| FNSETPM | An 80287 instruction that put the coprocessor in protected mode; later x87 units ignore it, and XED decodes it as a no-op. | x87 |
| FNSTCW | Stores the x87 control word to 16 bits of memory; FSTCW is FWAIT followed by it. | x87 |
| FNSTENV | Stores the x87 environment to memory, then masks all x87 exceptions; FSTENV is FWAIT followed by it. | x87 |
| FNSTSW | Stores the x87 status word to 16 bits of memory or to AX; FSTSW is FWAIT followed by it. | x87 |
| FPATAN | Stores the arctangent of ST(1) divided by ST(0), in radians, in ST(1) and pops the register stack. | x87 |
| FPREM | Stores in ST(0) the partial remainder of ST(0) divided by ST(1) with a truncated quotient, as C's fmod gives; C2 says whether to repeat. | x87 |
| FPREM1 | Stores in ST(0) the partial IEEE 754 remainder of ST(0) divided by ST(1), with the quotient rounded to nearest; C2 says whether to repeat. | x87 |
| FPTAN | Replaces ST(0), an angle in radians of magnitude below 2^63, with its tangent and then pushes 1.0. | x87 |
| FRNDINT | Rounds ST(0) to an integral value in the rounding mode of the x87 control word. | x87 |
| FRSTOR | Loads the x87 environment and data registers from memory that FSAVE or FNSAVE stored. | x87 |
| FSCALE | Multiplies ST(0) by 2 to the power of ST(1) truncated to an integer. | x87 |
| FSIN | Replaces ST(0), an angle in radians of magnitude below 2^63, with its sine; C2 reports an operand out of range. | x87 |
| FSINCOS | Replaces ST(0), an angle in radians, with its sine and pushes its cosine, so that ST(0) holds the cosine and ST(1) the sine. | x87 |
| FSQRT | Replaces ST(0) with its square root. | x87 |
| FST | Copies ST(0) to a 32- or 64-bit float in memory, rounding it, or to ST(i). | x87 |
| FSTP | Copies ST(0) to a 32-, 64- or 80-bit float in memory or to ST(i) and pops the register stack. | x87 |
| FSUB | Subtracts a float in memory from ST(0), or ST(i) from ST(0) or ST(0) from ST(i), into the minuend's register. | x87 |
| FSUBP | Subtracts ST(0) from ST(i), stores the difference in ST(i) and pops the register stack. | x87 |
| FSUBR | Subtracts ST(0) from a float in memory, or ST(0) from ST(i) into ST(0), or ST(i) from ST(0) into ST(i): FSUB with the operands swapped. | x87 |
| FSUBRP | Subtracts ST(i) from ST(0), stores the difference in ST(i) and pops the register stack. | x87 |
| FTST | Compares ST(0) with 0.0 and sets C0, C2 and C3 of the x87 status word. | x87 |
| FUCOM | Compares ST(0) with ST(i) and sets C0, C2 and C3 of the x87 status word; only a signaling NaN is an invalid operation. | x87 |
| FUCOMI | Compares ST(0) with ST(i) and sets ZF, PF and CF in EFLAGS; only a signaling NaN is an invalid operation. | x87 |
| FUCOMIP | Compares ST(0) with ST(i) like FUCOMI, setting ZF, PF and CF, then pops the register stack. | x87 |
| FUCOMP | Compares ST(0) with ST(i) like FUCOM, then pops the register stack. | x87 |
| FUCOMPP | Compares ST(0) with ST(1) like FUCOM, then pops the register stack twice. | x87 |
| FWAIT | Waits for the x87 unit and raises any pending unmasked x87 exception; WAIT is another name for it. | x87 |
| FXAM | Classifies ST(0) as empty, zero, normal, denormal, infinity, NaN or unsupported in C0, C2 and C3, with its sign in C1. | x87 |
| FXCH | Exchanges ST(0) with ST(i), ST(1) if no operand is given. | x87 |
| FXRSTOR | Restores the x87, MMX and SSE registers and MXCSR from the 512-byte area that FXSAVE wrote; FXRSTOR64 reads the 64-bit form. | FXSR |
| FXSAVE | Saves the x87, MMX and SSE registers and MXCSR to a 16-byte aligned 512-byte area; FXSAVE64 stores the x87 pointers as 64-bit values. | FXSR |
| FXTRACT | Splits ST(0) into its exponent, left in ST(1), and its significand, pushed as the new ST(0). | x87 |
| FYL2X | Stores ST(1) times log2(ST(0)) in ST(1) and pops the register stack. | x87 |
| FYL2XP1 | Stores ST(1) times log2(ST(0) + 1) in ST(1) and pops; for ST(0) near zero, where it is more accurate than FYL2X. | x87 |
| GETSEC | Performs the Safer Mode Extensions leaf function that EAX selects, such as SENTER, which launches an Intel TXT measured environment. | SMX |
| GETSEC[CAPABILITIES] | Returns a bit for each GETSEC leaf the processor supports and one for an Intel TXT chipset; any privilege level may run it. | SMX |
| GETSEC[ENTERACCS] | Loads the authenticated code module at the physical address in EBX, checks its signature with the chipset's key and runs it. | SMX |
| GETSEC[EXITAC] | Leaves authenticated code execution mode and continues at the address in EBX; an authenticated code module ends with it. | SMX |
| GETSEC[SENTER] | Launches a measured environment: authenticates the module at the physical address in EBX and gathers the other logical processors. | SMX |
| GETSEC[SEXIT] | Ends the measured environment that SENTER launched, signalling every logical processor of the platform. | SMX |
| GETSEC[PARAMETERS] | Returns one SMX parameter per index in EBX, such as the versions of authenticated code modules that the processor accepts. | SMX |
| GETSEC[SMCTRL] | Performs the SMX mode control that EBX selects; the only one, 0, unmasks SMIs after a measured launch. | SMX |
| GETSEC[WAKEUP] | Wakes the other logical processors from the sleep state that the SENTER rendezvous left them in, so that they join the measured environment. | SMX |
| GF2P8AFFINEINVQB | Inverts each byte in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant. | GFNI |
| GF2P8AFFINEQB | Applies an affine transformation to each byte, given by an 8x8 bit matrix from the source and an immediate constant. | GFNI |
| GF2P8MULB | Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1. | GFNI |
| HADDPD | Adds the two doubles within each source, the destination's sum going low and the source's high; SSE3. | SSE3 |
| HADDPS | Adds adjacent pairs of singles within each source, the destination's two sums going low and the source's high; SSE3. | SSE3 |
| HLT | Stops the processor until an interrupt, NMI or reset arrives, as an idle loop does; ring 0 only. | System |
| HRESET | Resets the parts of the processor's prediction history that EAX selects and the operating system enabled in IA32_HRESET_ENABLE; allowed only in ring 0. | HRESET |
| HSUBPD | Subtracts the high double from the low one within each source, the destination's result going low; SSE3. | SSE3 |
| HSUBPS | Subtracts the odd single from the even one in adjacent pairs of each source, the destination's results going low; SSE3. | SSE3 |
| IBHF | Indirect branch history fence: in ring 0 with BHI_DIS_S set, stops older branch history from steering later indirect branches; a no-op without BHI_CTRL. | IBHF |
| IDIV | Divides a signed double-width dividend in rDX:rAX (AX for bytes) by the operand into quotient and remainder; APX adds a form that keeps the flags. | General-purpose, APX |
| IMUL | Multiplies signed integers in one-, two- and three-operand forms; APX adds new-destination, flag-preserving and zero-upper immediate forms. | General-purpose, APX |
| IN | Reads a byte, word or doubleword from an I/O port, given as an immediate or in DX, into AL, AX or EAX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| INC | Adds one to an operand without changing the carry flag; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| INCSSPD | Pops and discards the number of 4-byte shadow-stack entries given in the low byte of a register, as unwinding the stack needs; CET. | CET |
| INCSSPQ | Pops and discards the number of 8-byte shadow-stack entries given in the low byte of a register, as unwinding the stack needs; CET. | CET |
| INS | Reads a byte, word or doubleword from the I/O port in DX into memory at [RDI] and steps RDI; REP repeats it RCX times. | General-purpose |
| INSERTPS | Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements; SSE4.1. | SSE4.1 |
| INSERTQ | Inserts the low bits of one XMM register as a bit field into the low quadword of another; SSE4a. | SSE4a |
| INT | Raises the software interrupt whose vector is the immediate, calling its handler through the IDT, as 32-bit Linux system calls do with INT 80h. | General-purpose |
| INT1 | Raises a debug exception (#DB) with the one-byte opcode F1, meant for hardware debuggers; also known as ICEBP. | General-purpose |
| INT3 | Raises a breakpoint exception (#BP) with the one-byte opcode CC, which debuggers write over an instruction to set a breakpoint. | General-purpose |
| INTO | Raises an overflow exception (#OF) if the overflow flag is set; not in 64-bit mode. | General-purpose |
| INVD | Invalidates the caches without writing modified lines back, so their data is lost; ring 0 only. | System |
| INVEPT | Invalidates cached translations derived from a VMX guest's extended page tables, for one EPT context or all of them. | VMX, APX |
| INVLPG | Invalidates the TLB entries of the page that holds a memory address, after the kernel changed its mapping; ring 0 only. | System |
| INVLPGA | Invalidates the TLB entry of the page at the address in rAX for the address space ID in ECX; AMD SVM. | SVM |
| INVLPGB | Invalidates TLB entries that a descriptor in rAX and EDX selects on every processor of the system, not just this one. | INVLPGB |
| INVPCID | Invalidates TLB entries and paging-structure caches for one address, one process-context identifier or all of them, as the type in a register selects. | INVPCID, APX |
| INVVPID | Invalidates cached translations tagged with a VMX virtual-processor identifier (VPID), for one address, one VPID or all of them. | VMX, APX |
| IRET | Returns from an interrupt or exception handler, popping the instruction pointer, CS and the flags, and in 64-bit mode RSP and SS too. | General-purpose |
| Jcc | Jumps to a relative target if a condition on the flags holds, such as JZ when ZF is set or JL when SF differs from OF. | General-purpose |
| JCXZ | Jumps to a short relative target if CX is zero, without testing or changing the flags; not in 64-bit mode. | General-purpose |
| JECXZ | Jumps to a short relative target if ECX is zero, without testing or changing the flags. | General-purpose |
| JMP | Jumps to a relative target, one in a register or memory, or a far pointer that also changes the code segment. | General-purpose |
| JMPABS | APX jump to a 64-bit absolute address given as an immediate, encoded with a REX2 prefix as an 11-byte instruction. | APX |
| JRCXZ | Jumps to a short relative target if RCX is zero, without testing or changing the flags; 64-bit mode only. | General-purpose |
| KADDB | Adds two 8-bit mask registers as unsigned integers. | AVX10.1 |
| KADDD | Adds two 32-bit mask registers as unsigned integers. | AVX10.1 |
| KADDQ | Adds two 64-bit mask registers as unsigned integers. | AVX10.1 |
| KADDW | Adds two 16-bit mask registers as unsigned integers. | AVX10.1 |
| KANDB | Computes the bitwise AND of two 8-bit masks. | AVX10.1 |
| KANDD | Computes the bitwise AND of two 32-bit masks. | AVX10.1 |
| KANDNB | Computes the bitwise AND of the inverted first 8-bit mask with the second. | AVX10.1 |
| KANDND | Computes the bitwise AND of the inverted first 32-bit mask with the second. | AVX10.1 |
| KANDNQ | Computes the bitwise AND of the inverted first 64-bit mask with the second. | AVX10.1 |
| KANDNW | Computes the bitwise AND of the inverted first 16-bit mask with the second. | AVX10.1 |
| KANDQ | Computes the bitwise AND of two 64-bit masks. | AVX10.1 |
| KANDW | Computes the bitwise AND of two 16-bit masks. | AVX10.1 |
| KMOVB | Moves an 8-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVD | Moves a 32-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVQ | Moves a 64-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KMOVW | Moves a 16-bit mask between mask registers, general-purpose registers and memory; APX adds EVEX forms that reach the extended general-purpose registers. | AVX10.1, APX |
| KNOTB | Inverts every bit of an 8-bit mask. | AVX10.1 |
| KNOTD | Inverts every bit of a 32-bit mask. | AVX10.1 |
| KNOTQ | Inverts every bit of a 64-bit mask. | AVX10.1 |
| KNOTW | Inverts every bit of a 16-bit mask. | AVX10.1 |
| KORB | Computes the bitwise OR of two 8-bit masks. | AVX10.1 |
| KORD | Computes the bitwise OR of two 32-bit masks. | AVX10.1 |
| KORQ | Computes the bitwise OR of two 64-bit masks. | AVX10.1 |
| KORTESTB | ORs two 8-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTD | ORs two 32-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTQ | ORs two 64-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORTESTW | ORs two 16-bit masks and sets ZF if the result is all zeros and CF if it is all ones. | AVX10.1 |
| KORW | Computes the bitwise OR of two 16-bit masks. | AVX10.1 |
| KSHIFTLB | Shifts an 8-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLD | Shifts a 32-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLQ | Shifts a 64-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTLW | Shifts a 16-bit mask left by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRB | Shifts an 8-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRD | Shifts a 32-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRQ | Shifts a 64-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KSHIFTRW | Shifts a 16-bit mask right by an immediate count, filling with zeros. | AVX10.1 |
| KTESTB | Sets ZF if the AND of two 8-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTD | Sets ZF if the AND of two 32-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTQ | Sets ZF if the AND of two 64-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KTESTW | Sets ZF if the AND of two 16-bit masks is zero and CF if the AND of the inverted first with the second is zero. | AVX10.1 |
| KUNPCKBW | Joins the low 8 bits of two masks into a 16-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKDQ | Joins the low 32 bits of two masks into a 64-bit mask, the second source forming the low half. | AVX10.1 |
| KUNPCKWD | Joins the low 16 bits of two masks into a 32-bit mask, the second source forming the low half. | AVX10.1 |
| KXNORB | Computes the bitwise XNOR of two 8-bit masks. | AVX10.1 |
| KXNORD | Computes the bitwise XNOR of two 32-bit masks. | AVX10.1 |
| KXNORQ | Computes the bitwise XNOR of two 64-bit masks. | AVX10.1 |
| KXNORW | Computes the bitwise XNOR of two 16-bit masks. | AVX10.1 |
| KXORB | Computes the bitwise XOR of two 8-bit masks. | AVX10.1 |
| KXORD | Computes the bitwise XOR of two 32-bit masks. | AVX10.1 |
| KXORQ | Computes the bitwise XOR of two 64-bit masks. | AVX10.1 |
| KXORW | Computes the bitwise XOR of two 16-bit masks. | AVX10.1 |
| LAHF | Copies SF, ZF, AF, PF and CF into bits 7, 6, 4, 2 and 0 of AH; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| LAR | Loads the access rights of the segment descriptor that a selector names and sets ZF, if the descriptor is visible at this privilege level. | System |
| LDDQU | Loads 128 unaligned bits into an XMM register like MOVDQU, but may read more bytes around them, for loads across cache lines; SSE3. | SSE3 |
| LDMXCSR | Loads the MXCSR register, the SSE control and status bits, from memory. | SSE |
| LDS | Loads a far pointer from memory into a register and DS; not in 64-bit mode, where its opcode C5 starts a VEX prefix. | General-purpose |
| LDTILECFG | Loads the AMX tile configuration (palette, rows and bytes per row of each tile) from a 64-byte memory block and zeroes the tile registers. | AMX-TILE, ACE, APX |
| LEA | Computes the address of a memory operand into a register without accessing memory, which compilers also use for arithmetic such as x*5+3. | General-purpose |
| LEAVE | Releases a stack frame: copies the frame pointer into the stack pointer, then pops the caller's frame pointer. | General-purpose |
| LES | Loads a far pointer from memory into a register and ES; not in 64-bit mode, where its opcode C4 starts a VEX prefix. | General-purpose |
| LFENCE | Waits until all earlier instructions have completed locally before any later one starts, which also bars speculative execution. | SSE2 |
| LFS | Loads a far pointer from memory into a register and FS. | General-purpose |
| LGDT | Loads the base and limit of the global descriptor table into GDTR from memory; ring 0 only. | System |
| LGS | Loads a far pointer from memory into a register and GS. | General-purpose |
| LIDT | Loads the base and limit of the interrupt descriptor table into IDTR from memory; ring 0 only. | System |
| LKGS | Loads GS from a selector but puts the descriptor's base in the IA32_KERNEL_GS_BASE MSR instead of the GS base; ring 0 of 64-bit mode only. | LKGS |
| LLDT | Loads the local descriptor table register from a selector of an LDT descriptor in the GDT; ring 0 only. | System |
| LLWPCB | Loads the address of a Lightweight Profiling control block from a register and starts profiling with it; LWP. | LWP |
| LMSW | Loads the low four bits of CR0 (PE, MP, EM and TS) from a word, the 80286's way into protected mode; ring 0 only. | System |
| LOADIWKEY | Loads the internal wrapping key of Key Locker from XMM registers; the key cannot be read back. Ring 0 only. | Key Locker |
| LODS | Loads the element at [RSI] into AL, AX, EAX or RAX and steps RSI up or down, as the direction flag says. | General-purpose |
| LOOP | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero. | General-purpose |
| LOOPE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is set. | General-purpose |
| LOOPNE | Decrements RCX, ECX or CX without changing the flags and jumps to a short relative target if the count is not zero and ZF is clear. | General-purpose |
| LSL | Loads the limit of the segment descriptor that a selector names and sets ZF, if the descriptor is visible at this privilege level. | System |
| LSS | Loads a far pointer from memory into a register and SS, switching the stack segment and pointer with one instruction. | General-purpose |
| LTR | Loads the task register from a selector of a TSS descriptor in the GDT and marks that TSS busy; ring 0 only. | System |
| LWPINS | Inserts a record with a value of the program's choosing into the Lightweight Profiling ring buffer; LWP. | LWP |
| LWPVAL | Counts a programmed value sample event of Lightweight Profiling and records it when its counter runs out; LWP. | LWP |
| LZCNT | Counts the leading zero bits of an operand; APX adds a form that leaves the flags unchanged. | LZCNT, APX |
| MASKMOVDQU | Stores the bytes of an XMM register whose mask byte in a second register has its top bit set to [RDI], non-temporally. | SSE2 |
| MASKMOVQ | Stores the bytes of an MMX register whose mask byte in a second MMX register has its top bit set to [RDI], non-temporally; SSE. | SSE |
| MAXPD | Returns the larger of each pair of packed doubles, or the source element if either is NaN or both are zero. | SSE2 |
| MAXPS | Returns the larger of each pair of packed singles, or the source element if either is NaN or both are zero. | SSE |
| MAXSD | Returns the larger of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept. | SSE2 |
| MAXSS | Returns the larger of the low singles, or the source's if either is NaN or both are zero; the other elements are kept. | SSE |
| MCOMMIT | Waits until earlier stores to memory with delayed error reporting have completed, and clears CF if any of them failed. | MCOMMIT |
| MFENCE | Makes all earlier loads and stores globally visible before any later load or store, a full memory barrier. | SSE2 |
| MINPD | Returns the smaller of each pair of packed doubles, or the source element if either is NaN or both are zero. | SSE2 |
| MINPS | Returns the smaller of each pair of packed singles, or the source element if either is NaN or both are zero. | SSE |
| MINSD | Returns the smaller of the low doubles, or the source's if either is NaN or both are zero; the upper half is kept. | SSE2 |
| MINSS | Returns the smaller of the low singles, or the source's if either is NaN or both are zero; the other elements are kept. | SSE |
| MONITOR | Arms the address monitor on the range holding the address in RAX, so that a later MWAIT waits for a store to it; ring 0 only. | MONITOR/MWAIT |
| MONITORX | Sets up the address range that MWAITX waits on, like MONITOR but usable at any privilege level. | MONITORX |
| MONTMUL | Performs a Montgomery multiplication in the PadLock Montgomery Multiplier, on operands that a block at [ESI] describes; VIA PadLock. | VIA PadLock |
| MOV | Copies data between registers, memory and immediates, and moves segment, control and debug registers; those last two only in ring 0. | General-purpose |
| MOVAPD | Moves packed doubles between XMM registers and memory, which must be aligned to 16 bytes. | SSE2 |
| MOVAPS | Moves packed singles between XMM registers and memory, which must be aligned to 16 bytes. | SSE |
| MOVBE | Loads or stores a 16-, 32- or 64-bit value with its byte order reversed; APX adds a register-to-register form. | MOVBE, APX |
| MOVD | Moves 32 bits between an MMX or XMM register and a general-purpose register or memory, zeroing the rest of a vector register. | SSE2, MMX |
| MOVDDUP | Loads or copies a double and duplicates it into both halves of an XMM register; SSE3. | SSE3 |
| MOVDIR64B | Copies 64 bytes from memory to a 64-byte-aligned destination as one direct store that is written atomically and bypasses the caches. | MOVDIR64B, APX |
| MOVDIRI | Stores a 32- or 64-bit register to memory as a direct store that bypasses the caches. | MOVDIRI, APX |
| MOVDQ2Q | Copies the low quadword of an XMM register to an MMX register. | SSE2 |
| MOVDQA | Moves 128 bits of integer data between XMM registers and memory, which must be aligned to 16 bytes. | SSE2 |
| MOVDQU | Moves 128 bits of integer data between XMM registers and memory without an alignment requirement. | SSE2 |
| MOVHLPS | Copies the high two singles of the source into the low half of the destination XMM register. | SSE |
| MOVHPD | Loads a double from memory into the high half of an XMM register, or stores the high double to memory. | SSE2 |
| MOVHPS | Loads two singles from memory into the high half of an XMM register, or stores the high two to memory. | SSE |
| MOVLHPS | Copies the low two singles of the source into the high half of the destination XMM register. | SSE |
| MOVLPD | Loads a double from memory into the low half of an XMM register, or stores the low double to memory. | SSE2 |
| MOVLPS | Loads two singles from memory into the low half of an XMM register, or stores the low two to memory. | SSE |
| MOVMSKPD | Copies the sign bits of two packed doubles into the low bits of a general-purpose register. | SSE2 |
| MOVMSKPS | Copies the sign bits of four packed singles into the low bits of a general-purpose register. | SSE |
| MOVNTDQ | Stores an XMM register to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE2 |
| MOVNTDQA | Loads 16 aligned bytes with a non-temporal hint, which lets it read write-combining memory efficiently; SSE4.1. | SSE4.1 |
| MOVNTI | Stores a general-purpose register to memory with a non-temporal hint that avoids polluting the caches; SSE2. | SSE2 |
| MOVNTPD | Stores packed doubles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE2 |
| MOVNTPS | Stores packed singles to 16-byte aligned memory with a non-temporal hint that avoids polluting the caches. | SSE |
| MOVNTQ | Stores an MMX register to memory with a non-temporal hint, which lets the write bypass the caches; SSE. | SSE |
| MOVNTSD | Stores the low double of an XMM register to memory with a non-temporal hint; SSE4a. | SSE4a |
| MOVNTSS | Stores the low single of an XMM register to memory with a non-temporal hint; SSE4a. | SSE4a |
| MOVQ | Moves 64 bits between MMX or XMM registers, general-purpose registers and memory, zeroing the rest of an XMM destination. | SSE2, MMX |
| MOVQ2DQ | Copies an MMX register to the low quadword of an XMM register and zeroes the high quadword. | SSE2 |
| MOVRS | Loads a register from memory with a hint that other cores are likely to read the same data before it is written. | MOVRS, APX |
| MOVS | Copies the element at [RSI] to [RDI] and steps both pointers; REP MOVS copies RCX elements, the classic memcpy. | General-purpose |
| MOVSD | Moves the low double between XMM registers or to and from memory; a load zeroes the upper half, a register move keeps it. | SSE2 |
| MOVSHDUP | Duplicates each odd-numbered single into the even position below it; SSE3. | SSE3 |
| MOVSLDUP | Duplicates each even-numbered single into the odd position above it; SSE3. | SSE3 |
| MOVSS | Moves the low single between XMM registers or to and from memory; a load zeroes the rest, a register move keeps it. | SSE |
| MOVSX | Copies a signed byte or word into a wider register, extending its sign bit. | General-purpose |
| MOVSXD | Sign-extends a 32-bit register or memory operand into a 64-bit register (AT&T movslq); 64-bit mode only, where it took over ARPL's opcode. | General-purpose |
| MOVUPD | Moves packed doubles between XMM registers and memory without an alignment requirement. | SSE2 |
| MOVUPS | Moves packed singles between XMM registers and memory without an alignment requirement. | SSE |
| MOVZX | Copies an unsigned byte or word into a wider register, filling the upper bits with zeros. | General-purpose |
| MPSADBW | Computes eight word sums of absolute differences between a 4-byte block of the source and sliding blocks of the destination; SSE4.1. | SSE4.1 |
| MUL | Multiplies unsigned integers, producing a double-width result in rDX:rAX (AX for bytes); APX adds a form that leaves the flags unchanged. | General-purpose, APX |
| MULPD | Multiplies the two packed doubles of the destination XMM register by those of the source. | SSE2 |
| MULPS | Multiplies the four packed singles of the destination XMM register by those of the source. | SSE |
| MULSD | Multiplies the low double of the destination by the low double of the source; the upper half is kept. | SSE2 |
| MULSS | Multiplies the low single of the destination by the low single of the source; the upper three elements are kept. | SSE |
| MULX | Multiplies rDX by an unsigned operand and writes the high and low halves of the product to two registers without touching the flags. | BMI2, APX |
| MWAIT | Waits in an optimized state that EAX hints at until the monitored range is written or an interrupt arrives; ring 0 only. | MONITOR/MWAIT |
| MWAITX | Waits until a store hits the range that MONITORX set up, or a timeout in EBX expires, at any privilege level. | MONITORX |
| NEG | Replaces an operand with its two's complement; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| NOP | Does nothing: 90 and the multi-byte 0F 1F forms pad code for alignment, and other opcodes of 0F 18 to 0F 1F are reserved to decode as NOPs. | General-purpose, PREFETCHW |
| NOT | Inverts every bit of an operand without changing the flags; APX adds a three-operand form. | General-purpose, APX |
| OR | Computes the bitwise OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ORPD | Computes the bitwise OR of two XMM operands, as packed doubles. | SSE2 |
| ORPS | Computes the bitwise OR of two XMM operands, as packed singles. | SSE |
| OUT | Writes AL, AX or EAX to an I/O port, given as an immediate or in DX, if IOPL or the TSS permission bitmap allows. | General-purpose |
| OUTS | Writes a byte, word or doubleword from memory at [RSI] to the I/O port in DX and steps RSI; REP repeats it RCX times. | General-purpose |
| PABSB | Computes the absolute values of packed signed bytes of an MMX or XMM operand; SSSE3. | SSSE3 |
| PABSD | Computes the absolute values of packed signed doublewords of an MMX or XMM operand; SSSE3. | SSSE3 |
| PABSW | Computes the absolute values of packed signed words of an MMX or XMM operand; SSSE3. | SSSE3 |
| PACKSSDW | Narrows signed doublewords of two MMX or XMM operands to words with signed saturation. | MMX, SSE2 |
| PACKSSWB | Narrows signed words of two MMX or XMM operands to bytes with signed saturation. | MMX, SSE2 |
| PACKUSDW | Narrows signed doublewords of two XMM operands to words with unsigned saturation; SSE4.1. | SSE4.1 |
| PACKUSWB | Narrows signed words of two MMX or XMM operands to bytes with unsigned saturation. | MMX, SSE2 |
| PADDB | Adds packed bytes of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PADDD | Adds packed doublewords of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PADDQ | Adds packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2. | SSE2 |
| PADDSB | Adds packed signed bytes of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PADDSW | Adds packed signed words of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PADDUSB | Adds packed unsigned bytes of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PADDUSW | Adds packed unsigned words of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PADDW | Adds packed words of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PALIGNR | Concatenates two MMX or XMM operands and extracts a register's worth of bytes at the byte offset an immediate gives; SSSE3. | SSSE3 |
| PAND | Computes the bitwise AND of two MMX or XMM operands. | MMX, SSE2 |
| PANDN | Computes the bitwise AND of the inverted destination with the source, in MMX or XMM registers. | MMX, SSE2 |
| PAUSE | Tells the processor it is in a spin-wait loop, which avoids a penalty on leaving the loop and saves power; a NOP before the Pentium 4. | General-purpose |
| PAVGB | Computes the rounded averages of packed unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PAVGUSB | Computes the averages of packed unsigned bytes of two MMX operands, rounded up; 3DNow!. | 3DNow! |
| PAVGW | Computes the rounded averages of packed unsigned words of MMX or XMM registers. | SSE, SSE2 |
| PBLENDVB | Picks each byte from the destination or the source by the top bit of the matching byte of XMM0; SSE4.1. | SSE4.1 |
| PBLENDW | Picks each word from the destination or the source, as a bit of an immediate says; SSE4.1. | SSE4.1 |
| PBNDKB | Encrypts and authenticates a 256-byte bind structure with a platform key, for PCONFIG to use in configuring Total Storage Encryption. | PBNDKB |
| PCLMULQDQ | Carry-less multiplies one quadword of each operand, chosen by an immediate, into a 128-bit product. | PCLMULQDQ |
| PCMPEQB | Compares packed bytes of MMX or XMM registers for equality, into all-ones or all-zeros bytes. | MMX, SSE2 |
| PCMPEQD | Compares packed doublewords of MMX or XMM registers for equality, into all-ones or all-zeros elements. | MMX, SSE2 |
| PCMPEQQ | Compares packed quadwords for equality, into all-ones or all-zeros quadwords; SSE4.1. | SSE4.1 |
| PCMPEQW | Compares packed words of MMX or XMM registers for equality, into all-ones or all-zeros words. | MMX, SSE2 |
| PCMPESTRI | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning an index in ECX; SSE4.2. | SSE4.2 |
| PCMPESTRM | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with REX.W) as an immediate says, returning a mask in XMM0; SSE4.2. | SSE4.2 |
| PCMPGTB | Tests packed signed bytes of MMX or XMM registers for greater than, into all-ones or all-zeros bytes. | MMX, SSE2 |
| PCMPGTD | Tests packed signed doublewords of MMX or XMM registers for greater than, into all-ones or all-zeros elements. | MMX, SSE2 |
| PCMPGTQ | Tests packed signed quadwords for greater than, into all-ones or all-zeros quadwords; SSE4.2. | SSE4.2 |
| PCMPGTW | Tests packed signed words of MMX or XMM registers for greater than, into all-ones or all-zeros words. | MMX, SSE2 |
| PCMPISTRI | Compares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; SSE4.2. | SSE4.2 |
| PCMPISTRM | Compares two zero-terminated strings in XMM registers as an immediate says, returning a bit or byte mask in XMM0; SSE4.2. | SSE4.2 |
| PCONFIG | Configures platform features, such as the keys of multi-key memory encryption, with the leaf function in EAX; ring 0 only. | PCONFIG |
| PDEP | Deposits the low bits of the source at the bit positions selected by a mask, clearing the others. | BMI2, APX |
| PEXT | Extracts the bits of the source at the positions selected by a mask and packs them into the low bits of the destination. | BMI2, APX |
| PEXTRB | Copies the byte an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRD | Copies the doubleword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRQ | Copies the quadword an immediate selects from an XMM register to a general-purpose register or memory; SSE4.1. | SSE4.1 |
| PEXTRW | Copies the word an immediate selects from an MMX or XMM register to a general-purpose register, or to memory (SSE4.1). | SSE, SSE2, SSE4.1 |
| PF2ID | Converts two packed singles of an MMX register or memory to signed doublewords, saturating out-of-range values; 3DNow!. | 3DNow! |
| PF2IW | Converts two packed singles to signed words, saturated and sign-extended to doublewords; AMD's 3DNow! extensions. | 3DNow! |
| PFACC | Adds the two singles of each MMX operand, the first operand's sum going to the low half of the result; 3DNow!. | 3DNow! |
| PFADD | Adds the two packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFCMPEQ | Compares the packed singles of two MMX operands for equality, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFCMPGE | Tests the packed singles of two MMX operands for greater than or equal, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFCMPGT | Tests the packed singles of two MMX operands for greater than, into all-ones or all-zeros doublewords; 3DNow!. | 3DNow! |
| PFMAX | Returns the larger of each pair of packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFMIN | Returns the smaller of each pair of packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFMUL | Multiplies the two packed singles of two MMX operands; 3DNow!. | 3DNow! |
| PFNACC | Subtracts the high single from the low one within each MMX operand, the first operand's result going low; 3DNow! extensions. | 3DNow! |
| PFPNACC | Subtracts the high single from the low one of the first operand and adds the singles of the second; 3DNow! extensions. | 3DNow! |
| PFRCP | Approximates the reciprocal of the low single of an MMX register or memory, into both halves of the destination; 3DNow!. | 3DNow! |
| PFRCPIT1 | Performs the first Newton-Raphson step that refines a PFRCP reciprocal approximation; 3DNow!. | 3DNow! |
| PFRCPIT2 | Performs the second and last Newton-Raphson step that refines a PFRCP or PFRSQRT approximation; 3DNow!. | 3DNow! |
| PFRSQIT1 | Performs the first Newton-Raphson step that refines a PFRSQRT reciprocal square root approximation; 3DNow!. | 3DNow! |
| PFRSQRT | Approximates the reciprocal square root of the low single of an MMX register or memory, into both halves; 3DNow!. | 3DNow! |
| PFSUB | Subtracts the packed singles of the second MMX operand from those of the first; 3DNow!. | 3DNow! |
| PFSUBR | Subtracts the packed singles of the first MMX operand from those of the second, into the first; 3DNow!. | 3DNow! |
| PHADDD | Adds adjacent pairs of doublewords within each MMX or XMM operand, the destination's sums going low; SSSE3. | SSSE3 |
| PHADDSW | Adds adjacent pairs of signed words within each operand with signed saturation, the destination's sums going low; SSSE3. | SSSE3 |
| PHADDW | Adds adjacent pairs of words within each MMX or XMM operand, the destination's sums going low; SSSE3. | SSSE3 |
| PHMINPOSUW | Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; SSE4.1. | SSE4.1 |
| PHSUBD | Subtracts the odd doubleword from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | SSSE3 |
| PHSUBSW | Subtracts the odd signed word from the even one in adjacent pairs of each operand with signed saturation; SSSE3. | SSSE3 |
| PHSUBW | Subtracts the odd word from the even one in adjacent pairs of each MMX or XMM operand; SSSE3. | SSSE3 |
| PI2FD | Converts two packed signed doublewords of an MMX register or memory to singles; 3DNow!. | 3DNow! |
| PI2FW | Converts the signed words in the low halves of two doublewords to packed singles; AMD's 3DNow! extensions. | 3DNow! |
| PINSRB | Inserts a byte from a general-purpose register or memory into an XMM register at the position an immediate gives; SSE4.1. | SSE4.1 |
| PINSRD | Inserts a doubleword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1. | SSE4.1 |
| PINSRQ | Inserts a quadword from a general-purpose register or memory into an XMM register where an immediate says; SSE4.1. | SSE4.1 |
| PINSRW | Inserts a word from a general-purpose register or memory into an MMX or XMM register at the position an immediate gives. | SSE, SSE2 |
| PMADDUBSW | Multiplies unsigned bytes of the destination by signed bytes of the source and adds adjacent products with signed saturation; SSSE3. | SSSE3 |
| PMADDWD | Multiplies packed signed words of MMX or XMM registers and adds adjacent products into doublewords. | MMX, SSE2 |
| PMAXSB | Returns the larger of each pair of signed bytes; SSE4.1. | SSE4.1 |
| PMAXSD | Returns the larger of each pair of signed doublewords; SSE4.1. | SSE4.1 |
| PMAXSW | Returns the larger of each pair of signed words of MMX or XMM registers. | SSE, SSE2 |
| PMAXUB | Returns the larger of each pair of unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PMAXUD | Returns the larger of each pair of unsigned doublewords; SSE4.1. | SSE4.1 |
| PMAXUW | Returns the larger of each pair of unsigned words; SSE4.1. | SSE4.1 |
| PMINSB | Returns the smaller of each pair of signed bytes; SSE4.1. | SSE4.1 |
| PMINSD | Returns the smaller of each pair of signed doublewords; SSE4.1. | SSE4.1 |
| PMINSW | Returns the smaller of each pair of signed words of MMX or XMM registers. | SSE, SSE2 |
| PMINUB | Returns the smaller of each pair of unsigned bytes of MMX or XMM registers. | SSE, SSE2 |
| PMINUD | Returns the smaller of each pair of unsigned doublewords; SSE4.1. | SSE4.1 |
| PMINUW | Returns the smaller of each pair of unsigned words; SSE4.1. | SSE4.1 |
| PMOVMSKB | Copies the top bit of each byte of an MMX or XMM register into the low bits of a general-purpose register. | SSE, SSE2 |
| PMOVSXBD | Sign-extends the four low bytes of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVSXBQ | Sign-extends the two low bytes of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVSXBW | Sign-extends the eight low bytes of the source to words; SSE4.1. | SSE4.1 |
| PMOVSXDQ | Sign-extends the two low doublewords of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVSXWD | Sign-extends the four low words of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVSXWQ | Sign-extends the two low words of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXBD | Zero-extends the four low bytes of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVZXBQ | Zero-extends the two low bytes of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXBW | Zero-extends the eight low bytes of the source to words; SSE4.1. | SSE4.1 |
| PMOVZXDQ | Zero-extends the two low doublewords of the source to quadwords; SSE4.1. | SSE4.1 |
| PMOVZXWD | Zero-extends the four low words of the source to doublewords; SSE4.1. | SSE4.1 |
| PMOVZXWQ | Zero-extends the two low words of the source to quadwords; SSE4.1. | SSE4.1 |
| PMULDQ | Multiplies the signed low doubleword of each quadword into 64-bit products; SSE4.1. | SSE4.1 |
| PMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result; SSSE3. | SSSE3 |
| PMULHRW | Multiplies packed signed words of two MMX operands and keeps the high 16 bits of each product, rounded; 3DNow!. | 3DNow! |
| PMULHUW | Multiplies packed unsigned words of MMX or XMM registers and keeps the high 16 bits of each product. | SSE, SSE2 |
| PMULHW | Multiplies packed signed words of MMX or XMM registers and keeps the high 16 bits of each product. | MMX, SSE2 |
| PMULLD | Multiplies packed doublewords and keeps the low 32 bits of each product; SSE4.1. | SSE4.1 |
| PMULLW | Multiplies packed words of MMX or XMM registers and keeps the low 16 bits of each product. | MMX, SSE2 |
| PMULUDQ | Multiplies the unsigned low doubleword of each quadword of MMX or XMM registers into 64-bit products; SSE2. | SSE2 |
| POP | Loads the value on top of the stack into a register, memory or a segment register and moves the stack pointer past it. | General-purpose |
| POP2 | APX instruction that pops two 64-bit registers from a 16-byte-aligned stack slot. | APX |
| POP2P | POP2 with APX's push-pop acceleration hint, marking it as the partner of a PUSH2P so the processor can forward the values without the memory round trip. | APX |
| POPA | Pops the eight general-purpose registers that PUSHA saved, 16-bit or with POPAD 32-bit, discarding the saved stack pointer; not in 64-bit mode. | General-purpose |
| POPCNT | Counts the bits that are set in an operand; APX adds a form that leaves the flags unchanged. | POPCNT, APX |
| POPF | Pops the flags from the stack, changing only those the privilege level allows; POPFQ, the 64-bit form, pops RFLAGS. | General-purpose |
| POPP | Pops a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of an earlier PUSHP. | APX |
| POR | Computes the bitwise OR of two MMX or XMM operands. | MMX, SSE2 |
| PREFETCH | Loads the cache line of a byte in memory into the first-level data cache ahead of use; AMD lets reserved 0F 0D forms act the same. | PREFETCHW |
| PREFETCHIT0 | Prefetches code at a RIP-relative address into all cache levels; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHIT1 | Prefetches code at a RIP-relative address into every cache level but L1; a no-op without RIP-relative addressing or on older processors. | PREFETCHI |
| PREFETCHNTA | Hints that the cache line holding a byte of memory should be fetched close to the processor while polluting the caches little. | SSE |
| PREFETCHRST2 | Prefetches data with a hint that several cores are likely to read it before it is written, into caches chosen for read sharing. | MOVRS |
| PREFETCHT0 | Hints that the cache line holding a byte of memory should be fetched into all levels of the cache hierarchy. | SSE |
| PREFETCHT1 | Hints that the cache line holding a byte of memory should be fetched into the second-level cache and higher. | SSE |
| PREFETCHT2 | Hints that the cache line holding a byte of memory should be fetched into the third-level cache and higher. | SSE |
| PREFETCHW | Loads the cache line of a byte in memory into the cache ahead of a write, in the modified state on AMD processors. | PREFETCHW |
| PREFETCHWT1 | Prefetches the cache line of a byte in memory into the second-level cache with intent to write, in exclusive state. | PREFETCHWT1 |
| PSADBW | Sums the absolute differences of unsigned bytes over each group of eight, into one 16-bit sum per quadword. | SSE, SSE2 |
| PSHUFB | Rearranges the bytes of an MMX or XMM register by an index byte per result, which zeroes the byte when its top bit is set; SSSE3. | SSSE3 |
| PSHUFD | Rearranges the four doublewords of an XMM operand as an immediate selects. | SSE2 |
| PSHUFHW | Rearranges the upper four words of an XMM operand as an immediate selects, copying the lower four. | SSE2 |
| PSHUFLW | Rearranges the lower four words of an XMM operand as an immediate selects, copying the upper four. | SSE2 |
| PSHUFW | Copies to an MMX register the words of another or of memory in the order four 2-bit fields of an immediate select; SSE. | SSE |
| PSIGNB | Negates, zeroes or keeps each signed byte of the destination as the matching source byte is negative, zero or positive; SSSE3. | SSSE3 |
| PSIGND | Negates, zeroes or keeps each doubleword of the destination as the matching source element is negative, zero or positive; SSSE3. | SSSE3 |
| PSIGNW | Negates, zeroes or keeps each signed word of the destination as the matching source word is negative, zero or positive; SSSE3. | SSSE3 |
| PSLLD | Shifts packed doublewords of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSLLDQ | Shifts an XMM register left by the number of bytes an immediate gives, filling with zeros. | SSE2 |
| PSLLQ | Shifts packed quadwords of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSLLW | Shifts packed words of an MMX or XMM register left by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSMASH | Splits the reverse map (RMP) entry of a 2-MByte page into the entries of its 512 4-KByte pages; SEV-SNP. | SEV-SNP |
| PSRAD | Shifts packed doublewords of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRAW | Shifts packed words of an MMX or XMM register right arithmetically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLD | Shifts packed doublewords of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLDQ | Shifts an XMM register right by the number of bytes an immediate gives, filling with zeros. | SSE2 |
| PSRLQ | Shifts packed quadwords of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSRLW | Shifts packed words of an MMX or XMM register right logically by a count from a register, memory or an immediate. | MMX, SSE2 |
| PSUBB | Subtracts packed bytes of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSUBD | Subtracts packed doublewords of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSUBQ | Subtracts packed quadwords of MMX or XMM registers, wrapping around on overflow; SSE2. | SSE2 |
| PSUBSB | Subtracts packed signed bytes of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PSUBSW | Subtracts packed signed words of MMX or XMM registers with signed saturation. | MMX, SSE2 |
| PSUBUSB | Subtracts packed unsigned bytes of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PSUBUSW | Subtracts packed unsigned words of MMX or XMM registers with unsigned saturation. | MMX, SSE2 |
| PSUBW | Subtracts packed words of MMX or XMM registers, wrapping around on overflow. | MMX, SSE2 |
| PSWAPD | Swaps the two doublewords of an MMX register or memory into another MMX register; AMD's 3DNow! extensions. | 3DNow! |
| PTEST | Sets ZF if the AND of two XMM operands is all zeros and CF if the AND of the inverted destination with the source is; SSE4.1. | SSE4.1 |
| PTWRITE | Writes a 32- or 64-bit value from a register or memory into the Intel Processor Trace stream, when tracing records such packets. | PTWRITE |
| PUNPCKHBW | Interleaves the high bytes of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKHDQ | Interleaves the high doublewords of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKHQDQ | Interleaves the high quadwords of two XMM operands. | SSE2 |
| PUNPCKHWD | Interleaves the high words of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLBW | Interleaves the low bytes of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLDQ | Interleaves the low doublewords of two MMX or XMM operands. | MMX, SSE2 |
| PUNPCKLQDQ | Interleaves the low quadwords of two XMM operands. | SSE2 |
| PUNPCKLWD | Interleaves the low words of two MMX or XMM operands. | MMX, SSE2 |
| PUSH | Moves the stack pointer down and stores a register, memory operand, immediate or segment register on top of the stack. | General-purpose |
| PUSH2 | APX instruction that pushes two 64-bit registers to a 16-byte-aligned stack slot. | APX |
| PUSH2P | PUSH2 with APX's push-pop acceleration hint, marking it as the partner of a POP2P so the processor can forward the values without the memory round trip. | APX |
| PUSHA | Pushes the eight 16-bit general-purpose registers, or with PUSHAD the 32-bit ones, including the original stack pointer; not in 64-bit mode. | General-purpose |
| PUSHF | Pushes the flags onto the stack: FLAGS, EFLAGS with PUSHFD, or RFLAGS with PUSHFQ, the default in 64-bit mode. | General-purpose |
| PUSHP | Pushes a 64-bit register with APX's push-pop acceleration hint, marking it as the partner of a later POPP. | APX |
| PVALIDATE | Lets an SEV-SNP guest validate a page of its memory, or take the validation back, in the reverse map (RMP). | SEV-SNP |
| PXOR | Computes the bitwise XOR of two MMX or XMM operands; with the same register twice it zeroes it. | MMX, SSE2 |
| RCL | Rotates an operand left through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RCPPS | Approximates the reciprocals of four packed singles, with a relative error of at most 1.5 times 2^-12. | SSE |
| RCPSS | Approximates the reciprocal of the low single, with a relative error of at most 1.5 times 2^-12; the other elements are kept. | SSE |
| RCR | Rotates an operand right through the carry flag; APX adds a three-operand form. | General-purpose, APX |
| RDFSBASE | Reads the FS base, where x86-64 Linux keeps a thread's TLS pointer, into a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| RDGSBASE | Reads the GS base into a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| RDMSR | Reads a model-specific register into EDX:EAX, or with MSR_IMM into any 64-bit register from an MSR number given as an immediate; allowed only in ring 0. | System, MSR_IMM, APX |
| RDMSRLIST | Reads up to 64 model-specific registers whose addresses are listed in a table in memory, selected by a bit mask in RCX, into a second table. | MSRLIST |
| RDPID | Reads the processor ID that the kernel stored in IA32_TSC_AUX (on Linux, the CPU and node number) without reading the time-stamp counter. | RDPID |
| RDPKRU | Reads PKRU, the access- and write-disable bits of the 16 protection keys, into EAX; ECX must be zero. | PKU |
| RDPMC | Reads the performance counter that ECX selects into EDX:EAX; user code may run it only where the kernel set CR4.PCE. | System |
| RDPRU | Reads the processor register that ECX selects, MPERF or APERF, into EDX:EAX, at any privilege level unless CR4.TSD is set. | RDPRU |
| RDRAND | Returns a random number from the processor's hardware generator; CF=1 means the value is valid, CF=0 that none was ready. | RDRAND |
| RDSEED | Returns a random number straight from the processor's entropy source, to seed other generators; CF=1 means the value is valid, CF=0 that none was ready. | RDSEED |
| RDSSPD | Copies the low 32 bits of the shadow-stack pointer into a register; a NOP where shadow stacks are off, which code can test for. | CET |
| RDSSPQ | Copies the 64-bit shadow-stack pointer into a register; a NOP where shadow stacks are off, which code can test for. | CET |
| RDTSC | Reads the time-stamp counter into EDX:EAX, unordered with nearby instructions; user code may run it unless CR4.TSD is set. | System |
| RDTSCP | Reads the time-stamp counter into EDX:EAX and IA32_TSC_AUX into ECX, once all earlier instructions have executed. | RDTSCP |
| RET | Returns from a procedure: pops the return address (and CS for a far return) and optionally releases stack bytes of the caller's arguments. | General-purpose |
| RMPADJUST | Changes the permissions of a guest page for a less privileged VMPL in the reverse map (RMP); SEV-SNP. | SEV-SNP |
| RMPUPDATE | Writes a new reverse map (RMP) entry for a page, which the hypervisor uses to assign it to a guest; SEV-SNP. | SEV-SNP |
| ROL | Rotates an operand left; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| ROR | Rotates an operand right; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| RORX | Rotates the source right by an immediate count into a separate destination without touching the flags. | BMI2, APX |
| ROUNDPD | Rounds two packed doubles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1. | SSE4.1 |
| ROUNDPS | Rounds four packed singles to integral values with the rounding mode of an immediate or MXCSR; SSE4.1. | SSE4.1 |
| ROUNDSD | Rounds the low double of the source to an integral value, by an immediate or MXCSR; the upper half is kept; SSE4.1. | SSE4.1 |
| ROUNDSS | Rounds the low single of the source to an integral value, by an immediate or MXCSR; the other elements are kept; SSE4.1. | SSE4.1 |
| RSM | Returns from system-management mode to the interrupted program and restores its state; valid only in SMM. | System |
| RSQRTPS | Approximates the reciprocal square roots of four packed singles, with a relative error of at most 1.5 times 2^-12. | SSE |
| RSQRTSS | Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements are kept. | SSE |
| RSTORSSP | Switches the shadow-stack pointer to the one in a restore token in memory, the way user-space stack switching works under CET. | CET |
| SAHF | Stores bits 7, 6, 4, 2 and 0 of AH into SF, ZF, AF, PF and CF; 64-bit mode needs the LAHF-SAHF feature. | LAHF-SAHF |
| SALC | Sets AL to FFh if the carry flag is set and to 00h if not, like SBB AL, AL but without changing the flags; not in 64-bit mode. | General-purpose |
| SAR | Shifts an operand right, copying the sign bit into the vacated bits; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SARX | Shifts the source right arithmetically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SAVEPREVSSP | Pushes a restore token onto the shadow stack that RSTORSSP switched away from, so it can be resumed later; CET. | CET |
| SBB | Subtracts an integer and the carry flag, the step that chains multi-word subtractions; APX adds a three-operand form. | General-purpose, APX |
| SCAS | Compares AL, AX, EAX or RAX with the element at [RDI], setting the flags as CMP would, and steps RDI; REPNE SCAS searches for a value. | General-purpose |
| SEAMCALL | Calls the SEAM module (the Intel TDX module) from a hypervisor in VMX root operation, entering SEAM root operation. | TDX |
| SEAMOPS | Invokes a SEAM-specific operation; only software in SEAM root operation, the SEAM module, can execute it. | TDX |
| SEAMRET | Returns from the SEAM module in SEAM root operation to the hypervisor that called it with SEAMCALL. | TDX |
| SENDUIPI | Sends a user interprocessor interrupt through the entry of the user-interrupt target table that a register selects. | UINTR |
| SERIALIZE | Waits until earlier instructions have completed and their stores are visible before fetching the next, without the side effects of CPUID. | SERIALIZE |
| SETcc | Writes 1 or 0 to a byte depending on a condition on the flags; APX adds a form that also clears the rest of the destination register. | General-purpose, APX |
| SETSSBSY | Marks the supervisor shadow-stack token at IA32_PL0_SSP busy and loads the shadow-stack pointer from it; not with FRED. | CET |
| SFENCE | Makes all earlier stores globally visible before any later store, which orders non-temporal and write-combining stores. | SSE |
| SGDT | Stores the base and limit of the global descriptor table to memory; user code may run it unless CR4.UMIP is set. | System |
| SHA1MSG1 | Performs the first step of the SHA-1 message schedule, an XOR of message dwords, for the next four. | SHA |
| SHA1MSG2 | Performs the second step of the SHA-1 message schedule, finishing four message dwords with a rotate. | SHA |
| SHA1NEXTE | Computes the SHA-1 state variable E after four rounds from the state and adds it to the next four message dwords. | SHA |
| SHA1RNDS4 | Performs four rounds of SHA-1, with the round function and constant chosen by an immediate. | SHA |
| SHA256MSG1 | Performs the first step of the SHA-256 message schedule for the next four message dwords. | SHA |
| SHA256MSG2 | Performs the second step of the SHA-256 message schedule, finishing four message dwords. | SHA |
| SHA256RNDS2 | Performs two rounds of SHA-256, taking the message words plus round constants from XMM0. | SHA |
| SHL | Shifts an operand left, filling with zeros (SAL is the same instruction); APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLD | Shifts an operand left and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHLX | Shifts the source left by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SHR | Shifts an operand right, filling with zeros; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRD | Shifts an operand right and fills the vacated bits from a second register; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SHRX | Shifts the source right logically by a count in a register into a separate destination without touching the flags. | BMI2, APX |
| SHUFPD | Picks one double from each operand for the two result positions, as an immediate selects. | SSE2 |
| SHUFPS | Picks two singles from the destination for the low half and two from the source for the high half, as an immediate selects. | SSE |
| SIDT | Stores the base and limit of the interrupt descriptor table to memory; user code may run it unless CR4.UMIP is set. | System |
| SKINIT | Reinitializes the processor securely and starts the secure loader at the physical address in EAX after measuring it; AMD SVM. | SVM |
| SLDT | Stores the selector in the local descriptor table register to a register or memory; CR4.UMIP keeps it from user code. | System |
| SLWPCB | Stores the Lightweight Profiling state to memory and returns the address of its control block in a register; LWP. | LWP |
| SMSW | Stores the machine status word, the low bits of CR0, to a register or memory; CR4.UMIP keeps it from user code. | System |
| SQRTPD | Computes the square roots of two packed doubles. | SSE2 |
| SQRTPS | Computes the square roots of four packed singles. | SSE |
| SQRTSD | Computes the square root of the low double of the source into the low double of the destination; the upper half is kept. | SSE2 |
| SQRTSS | Computes the square root of the low single of the source into the destination; the upper three elements are kept. | SSE |
| STAC | Sets the alignment-check flag (AC), which lets the kernel reach user pages despite SMAP until CLAC clears it; ring 0 only. | SMAP |
| STC | Sets the carry flag (CF). | General-purpose |
| STD | Sets the direction flag (DF), so that string instructions step downward through memory. | General-purpose |
| STGI | Sets the global interrupt flag (GIF) again, letting external interrupts through; AMD SVM. | SVM |
| STI | Sets the interrupt flag (IF), accepting maskable interrupts after the next instruction; where CPL is above IOPL it faults or sets the virtual one instead. | General-purpose |
| STMXCSR | Stores the MXCSR register, the SSE control and status bits, to memory. | SSE |
| STOS | Stores AL, AX, EAX or RAX at [RDI] and steps RDI; REP STOS fills RCX elements, the classic memset. | General-purpose |
| STR | Stores the selector in the task register to a register or memory; CR4.UMIP keeps it from user code. | System |
| STTILECFG | Stores the current AMX tile configuration to a 64-byte memory block. | AMX-TILE, ACE, APX |
| STUI | Sets the user interrupt flag (UIF), so that pending user interrupts can be delivered right after it. | UINTR |
| SUB | Subtracts one integer from another and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| SUBPD | Subtracts the two packed doubles of the source from those of the destination XMM register. | SSE2 |
| SUBPS | Subtracts the four packed singles of the source from those of the destination XMM register. | SSE |
| SUBSD | Subtracts the low double of the source from the low double of the destination; the upper half is kept. | SSE2 |
| SUBSS | Subtracts the low single of the source from the low single of the destination; the upper three elements are kept. | SSE |
| SWAPGS | Exchanges the GS base with IA32_KERNEL_GS_BASE, so that a kernel entered by SYSCALL finds its per-CPU data; 64-bit mode, ring 0. | System |
| SYSCALL | Enters the kernel fast: saves RIP in RCX and RFLAGS in R11 and jumps to IA32_LSTAR at ring 0; the system call of 64-bit Linux. | SYSCALL/SYSRET |
| SYSENTER | Enters the kernel at the address and stack in the SYSENTER MSRs at ring 0, without saving a return point; used by 32-bit systems. | SYSENTER/SYSEXIT |
| SYSEXIT | Returns from a SYSENTER entry to ring 3 at the address in RDX or EDX, with the stack pointer in RCX or ECX; ring 0 only. | SYSENTER/SYSEXIT |
| SYSRET | Returns from SYSCALL to user mode, loading RIP from RCX and RFLAGS from R11; with REX.W to 64-bit code, without to 32-bit code. | SYSCALL/SYSRET |
| T1MSKC | Makes a mask of the trailing ones of the source, inverted (~x | (x + 1)); TBM. | TBM |
| TCMMIMFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the imaginary parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCMMRLFP16PS | Multiplies two tiles of complex half-precision numbers and accumulates the real parts of the products into a single-precision tile. | AMX-COMPLEX |
| TCVTROWD2PS | Moves one row of a tile to a ZMM register, converting its 32-bit integers to single precision. | AMX-AVX512, ACE |
| TCVTROWPS2BF16H | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2BF16L | Moves one row of a tile to a ZMM register, converting single precision to bfloat16 in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TCVTROWPS2PHH | Moves one row of a tile to a ZMM register, converting single precision to half precision in the high half of each dword and zeroing the low half. | AMX-AVX512, ACE |
| TCVTROWPS2PHL | Moves one row of a tile to a ZMM register, converting single precision to half precision in the low half of each dword and zeroing the high half. | AMX-AVX512, ACE |
| TDCALL | Calls the SEAM module from a trust domain, a guest in SEAM non-root operation, by a VM exit. | TDX |
| TDPBF16PS | Multiplies two tiles of bfloat16 pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-BF16 |
| TDPBF8PS | Multiplies two tiles of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBHF8PS | Multiplies a tile of E5M2 FP8 values by a tile of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPBSSD | Multiplies two tiles of signed bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBSUD | Multiplies a tile of signed bytes by a tile of unsigned bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUSD | Multiplies a tile of unsigned bytes by a tile of signed bytes and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPBUUD | Multiplies two tiles of unsigned bytes, four per dword, and accumulates each row-by-column dot product into a tile of 32-bit integers. | AMX-INT8 |
| TDPFP16PS | Multiplies two tiles of half-precision pairs and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP16 |
| TDPHBF8PS | Multiplies a tile of E4M3 FP8 values by a tile of E5M2 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TDPHF8PS | Multiplies two tiles of E4M3 FP8 values and accumulates each row-by-column dot product into a single-precision tile. | AMX-FP8 |
| TEST | ANDs two operands to set SF, ZF and PF and clear CF and OF, discarding the result; TEST with the same register twice checks it for zero. | General-purpose |
| TESTUI | Copies the user interrupt flag (UIF) into CF. | UINTR |
| TILELOADD | Loads a tile from memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILELOADDRS | Loads a tile from memory like TILELOADD, with a hint that other cores are likely to read the same data before it is written. | AMX-MOVRS, APX |
| TILELOADDRST1 | Loads a tile like TILELOADDRS, with the added hint that the data will be reused but need not stay in the nearest cache. | AMX-MOVRS, APX |
| TILELOADDT1 | Loads a tile like TILELOADD, with a hint that the data will be reused but need not stay in the nearest cache. | AMX-TILE, APX |
| TILEMOVCOL | ACE instruction that writes a ZMM register into one column of a tile register, the column chosen by an immediate or a register. | ACE |
| TILEMOVROW | Moves one row of a tile register to a ZMM register, or with ACE also the other way, the row chosen by an immediate or a register. | AMX-AVX512, ACE |
| TILERELEASE | Returns the AMX tile configuration and all tile data to their initial state: unconfigured and zero. | AMX-TILE, ACE |
| TILESTORED | Stores a tile to memory, row by row, with the row stride taken from the index register of its SIB-encoded address. | AMX-TILE, APX |
| TILEZERO | Sets every byte of a tile register to zero. | AMX-TILE, ACE |
| TLBSYNC | Waits until every processor has carried out the INVLPGB invalidations that this processor sent. | INVLPGB |
| TOP2BF16PS | ACE rank-2 outer product: adds the dot product of each bfloat16 pair of one ZMM source with each pair of the other to a single-precision tile. | ACE |
| TOP4BSSD | ACE outer product of two ZMM registers of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BSUD | ACE outer product of a ZMM register of signed bytes with one of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUSD | ACE outer product of a ZMM register of unsigned bytes with one of signed bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4BUUD | ACE outer product of two ZMM registers of unsigned bytes, four per dword, accumulated into a tile of 32-bit integers. | ACE |
| TOP4MXBF8PS | ACE outer product of E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBHF8PS | ACE outer product of E5M2 by E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXBSSPS | ACE outer product of two ZMM registers of MX INT8 values, scaled by the block scale register and accumulated into a single-precision tile. | ACE |
| TOP4MXHBF8PS | ACE outer product of E4M3 by E5M2 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TOP4MXHF8PS | ACE outer product of E4M3 FP8 vectors (OCP microscaling), scaled by the block scale register and added to a single-precision tile. | ACE |
| TPAUSE | Waits in a light or deeper power-saving state, chosen by bit 0 of a register, until the time-stamp counter reaches EDX:EAX. | WAITPKG |
| TZCNT | Counts the trailing zero bits of an operand; APX adds a form that leaves the flags unchanged. | BMI1, APX |
| TZMSK | Makes a mask of the trailing zeros of the source (~x & (x - 1)); TBM. | TBM |
| UCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | SSE2 |
| UCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | SSE |
| UD0 | Raises an invalid-opcode exception (#UD); some processors decode it without the ModR/M byte and operands that others read. | General-purpose |
| UD1 | Raises an invalid-opcode exception (#UD); its register and memory operands are decoded but not used. | General-purpose |
| UD2 | Raises an invalid-opcode exception (#UD); compilers emit it for __builtin_trap and code that must not be reached. | General-purpose |
| UDB | Raises an invalid-opcode exception (#UD) with the one-byte opcode D6, in 64-bit mode, where SALC is not available. | General-purpose |
| UIRET | Returns from a user-interrupt handler, popping the RIP, RFLAGS and RSP that delivery pushed, and sets UIF again. | UINTR |
| UMONITOR | Arms the address monitor on the range holding the address in a register, at any privilege level, for a later UMWAIT. | WAITPKG |
| UMWAIT | Waits in a light or deeper power-saving state until the UMONITOR range is written, an interrupt arrives or the TSC reaches EDX:EAX. | WAITPKG |
| UNPCKHPD | Interleaves the high doubles of two XMM operands. | SSE2 |
| UNPCKHPS | Interleaves the high two singles of two XMM operands. | SSE |
| UNPCKLPD | Interleaves the low doubles of two XMM operands. | SSE2 |
| UNPCKLPS | Interleaves the low two singles of two XMM operands. | SSE |
| URDMSR | Reads a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| UWRMSR | Writes a model-specific register from user mode, if the operating system allows that register in its user-MSR bitmap. | USER_MSR, APX |
| V4FMADDPS | Performs four fused multiply-adds of packed singles in a row, each with the next of four ZMM registers and the next single from memory. | AVX512_4FMAPS |
| V4FMADDSS | Performs four scalar fused multiply-adds of singles in a row, with the low singles of four consecutive registers and four from memory. | AVX512_4FMAPS |
| V4FNMADDPS | Performs four fused negated multiply-adds of packed singles in a row, with four consecutive ZMM registers and four singles from memory. | AVX512_4FMAPS |
| V4FNMADDSS | Performs four scalar fused negated multiply-adds of singles in a row, with four consecutive registers and four singles from memory. | AVX512_4FMAPS |
| VADDBF16 | Adds packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VADDPD | Adds packed doubles. | AVX, AVX10.1 |
| VADDPH | Adds packed half-precision values. | AVX10.1 |
| VADDPS | Adds packed singles. | AVX, AVX10.1 |
| VADDSD | Adds the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VADDSH | Adds the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VADDSS | Adds the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VADDSUBPD | Subtracts in the even-numbered doubles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination. | AVX |
| VADDSUBPS | Subtracts in the even-numbered singles and adds in the odd-numbered ones of two XMM or YMM sources, into a separate destination. | AVX |
| VAESDEC | Performs one round of AES decryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESDECLAST | Performs the last round of AES decryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESENC | Performs one round of AES encryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESENCLAST | Performs the last round of AES encryption on each 128-bit lane with the round key of the matching lane. | AES-NI, VAES, AVX10.1 |
| VAESIMC | Applies InvMixColumns to an AES round key in an XMM register, the VEX form of AESIMC. | AES-NI |
| VAESKEYGENASSIST | Computes the substituted and rotated words, with a round constant from an immediate, that AES key expansion needs; VEX form. | AES-NI |
| VALIGND | Concatenates two vectors and extracts one vector's worth of doublewords starting at an element offset given by an immediate. | AVX10.1 |
| VALIGNQ | Concatenates two vectors and extracts one vector's worth of quadwords starting at an element offset given by an immediate. | AVX10.1 |
| VANDNPD | Computes the bitwise AND of the inverted first source with the second, as packed doubles. | AVX, AVX10.1 |
| VANDNPS | Computes the bitwise AND of the inverted first source with the second, as packed singles. | AVX, AVX10.1 |
| VANDPD | Computes the bitwise AND of packed doubles. | AVX, AVX10.1 |
| VANDPS | Computes the bitwise AND of packed singles. | AVX, AVX10.1 |
| VBCSTNEBF162PS | Loads one bfloat16 value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBCSTNESH2PS | Loads one half-precision value from memory, converts it to single precision and broadcasts it to every element, without floating-point exceptions. | AVX-NE-CONVERT |
| VBLENDMPD | Picks each of the packed doubles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBLENDMPS | Picks each of the packed singles from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VBLENDPD | Picks each double from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination. | AVX |
| VBLENDPS | Picks each single from the first or the second source, as a bit of an immediate says, into a separate XMM or YMM destination. | AVX |
| VBLENDVPD | Picks each double from the first or the second source by the sign bit of the matching element of a fourth register operand. | AVX |
| VBLENDVPS | Picks each single from the first or the second source by the sign bit of the matching element of a fourth register operand. | AVX |
| VBROADCASTF128 | Loads 128 bits of floating-point data from memory into both halves of a YMM register. | AVX |
| VBROADCASTF32X2 | Copies a group of two singles (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTF32X4 | Copies a group of four singles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF32X8 | Copies a group of eight singles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTF64X2 | Copies a group of two doubles (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTF64X4 | Copies a group of four doubles (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI128 | Loads 128 bits of integer data from memory into both halves of a YMM register; AVX2. | AVX2 |
| VBROADCASTI32X2 | Copies a group of two doublewords (64 bits) from memory or a register to every such group of a vector. | AVX10.1 |
| VBROADCASTI32X4 | Copies a group of four doublewords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI32X8 | Copies a group of eight doublewords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTI64X2 | Copies a group of two quadwords (128 bits) from memory to every 128-bit block of a vector. | AVX10.1 |
| VBROADCASTI64X4 | Copies a group of four quadwords (256 bits) from memory to both halves of a ZMM register. | AVX10.1 |
| VBROADCASTSD | Copies one double from memory or an XMM register to every element of a vector. | AVX, AVX2, AVX10.1 |
| VBROADCASTSS | Copies one single from memory or an XMM register to every element of a vector. | AVX, AVX2, AVX10.1 |
| VCMPBF16 | Compares packed bfloat16 values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.2 |
| VCMPPD | Compares packed doubles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX10.1 |
| VCMPPH | Compares packed half-precision values with one of 32 predicates chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VCMPPS | Compares packed singles with one of 32 predicates chosen by an immediate; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX10.1 |
| VCMPSD | Compares the low doubles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX, AVX10.1 |
| VCMPSH | Compares the low half-precision values with one of 32 predicates chosen by an immediate and writes the result to a mask register. | AVX10.1 |
| VCMPSS | Compares the low singles with one of 32 predicates an immediate selects, into an all-ones or zero element (VEX) or a mask register (EVEX). | AVX, AVX10.1 |
| VCOMISBF16 | Compares the low bfloat16 values of two registers and sets ZF, PF and CF as COMISS does, without floating-point exceptions. | AVX10.2 |
| VCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX, AVX10.1 |
| VCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX10.1 |
| VCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; any NaN signals an invalid exception. | AVX, AVX10.1 |
| VCOMPRESSPD | Packs the doubles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMPRESSPS | Packs the singles selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VCOMXSD | Compares the low doubles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCOMXSH | Compares the low half-precision values and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation; NaNs signal invalid. | AVX10.2 |
| VCOMXSS | Compares the low singles and sets OF, SF, ZF, PF and CF so that one conditional jump can test any relation, unordered included; NaNs signal invalid. | AVX10.2 |
| VCVT2PH2BF8 | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2BF8S | Converts two vectors of half-precision values into one vector of E5M2 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PH2HF8 | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, rounding to nearest even. | AVX10.2 |
| VCVT2PH2HF8S | Converts two vectors of half-precision values into one vector of E4M3 FP8 values, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVT2PS2PHX | Converts two vectors of single-precision values into one vector of half-precision values, rounding as MXCSR or the instruction selects. | AVX10.2 |
| VCVTBF162IBS | Converts packed bfloat16 values to signed bytes with saturation, rounding to nearest even, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF162IUBS | Converts packed bfloat16 values to saturated unsigned bytes, rounding to nearest even, each in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTBF42HF8 | Converts packed 4-bit E2M1 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF62HF8 | Converts packed 6-bit E3M2 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTBF82BF4S | Converts packed E5M2 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82BF6S | Converts packed E5M2 FP8 values to the 6-bit E3M2 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTBF82PS | Converts packed E5M2 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTBIASPH2BF8 | Converts packed half-precision values to E5M2 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2BF8S | Converts packed half-precision values to E5M2 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPH2HF8 | Converts packed half-precision values to E4M3 FP8, adding an 8-bit bias below the kept bits before truncating, which allows stochastic rounding. | AVX10.2 |
| VCVTBIASPH2HF8S | Converts packed half-precision values to E4M3 FP8 with an 8-bit rounding bias, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTBIASPS2BF8 | Converts packed single-precision values to E5M2 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2BF8S | Converts packed single-precision values to E5M2 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTBIASPS2HF8 | Converts packed single-precision values to E4M3 FP8 with a rounding bias taken from another register, which allows stochastic rounding. | AVX10_V2_AUX |
| VCVTBIASPS2HF8S | Converts packed single-precision values to E4M3 FP8 with a rounding bias, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTDQ2PD | Converts packed signed doublewords to doubles. | AVX, AVX10.1 |
| VCVTDQ2PH | Converts packed signed doublewords to half precision. | AVX10.1 |
| VCVTDQ2PS | Converts packed signed doublewords to singles. | AVX, AVX10.1 |
| VCVTHF62HF8 | Converts packed 6-bit E2M3 floating-point values to E4M3 FP8, which is exact. | AVX10_V2_AUX |
| VCVTHF82BF4S | Converts packed E4M3 FP8 values to the 4-bit E2M1 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82HF6S | Converts packed E4M3 FP8 values to the 6-bit E2M3 format, rounding to nearest even and saturating out-of-range values. | AVX10_V2_AUX |
| VCVTHF82PH | Converts packed E4M3 FP8 values to half precision, which is exact. | AVX10.2 |
| VCVTHF82PS | Converts packed E4M3 FP8 values to single precision, which is exact. | AVX10_V2_AUX |
| VCVTNE2PS2BF16 | Converts two vectors of singles into one vector of bfloat16 values, rounding to nearest even. | AVX10.1 |
| VCVTNEEBF162PS | Converts the even-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEEPH2PS | Converts the even-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOBF162PS | Converts the odd-numbered bfloat16 values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEOPH2PS | Converts the odd-numbered half-precision values of a memory operand to single precision, without floating-point exceptions. | AVX-NE-CONVERT |
| VCVTNEPS2BF16 | Converts packed single-precision values to bfloat16, rounding to nearest even with denormals flushed to zero and without consulting MXCSR. | AVX-NE-CONVERT, AVX10.1 |
| VCVTPD2DQ | Converts packed doubles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPD2PH | Converts packed doubles to half precision, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2PS | Converts packed doubles to singles, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPD2QQ | Converts packed doubles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UDQ | Converts packed doubles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPD2UQQ | Converts packed doubles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2BF8 | Converts packed half-precision values to E5M2 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2BF8S | Converts packed half-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2DQ | Converts packed half-precision values to signed doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2HF8 | Converts packed half-precision values to E4M3 FP8, rounding to nearest even. | AVX10.2 |
| VCVTPH2HF8S | Converts packed half-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10.2 |
| VCVTPH2IBS | Converts packed half-precision values to signed bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2IUBS | Converts packed half-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTPH2PD | Converts packed half-precision values to doubles, which is exact. | AVX10.1 |
| VCVTPH2PS | Converts packed half-precision values to singles, which is exact. | F16C, AVX10.1 |
| VCVTPH2PSX | Converts packed half-precision values to singles like VCVTPH2PS, in the AVX512-FP16 form that also takes a broadcast memory source. | AVX10.1 |
| VCVTPH2QQ | Converts packed half-precision values to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UDQ | Converts packed half-precision values to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UQQ | Converts packed half-precision values to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2UW | Converts packed half-precision values to unsigned words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPH2W | Converts packed half-precision values to signed words, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2BF8 | Converts packed single-precision values to E5M2 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2BF8S | Converts packed single-precision values to E5M2 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2DQ | Converts packed singles to signed doublewords, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to nearest even. | AVX10_V2_AUX |
| VCVTPS2HF8S | Converts packed single-precision values to E4M3 FP8, saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTPS2IBS | Converts packed single-precision values to signed bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2IUBS | Converts packed single-precision values to unsigned bytes with saturation, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTPS2PD | Converts packed singles to doubles, which is exact. | AVX, AVX10.1 |
| VCVTPS2PH | Converts packed singles to half precision, rounding as an immediate or MXCSR selects. | F16C, AVX10.1 |
| VCVTPS2PHX | Converts packed singles to half precision like VCVTPS2PH, but with a broadcast source and embedded rounding instead of an immediate. | AVX10.1 |
| VCVTPS2QQ | Converts packed singles to signed quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UDQ | Converts packed singles to unsigned doublewords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTPS2UQQ | Converts packed singles to unsigned quadwords, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTQQ2PD | Converts packed signed quadwords to doubles. | AVX10.1 |
| VCVTQQ2PH | Converts packed signed quadwords to half precision. | AVX10.1 |
| VCVTQQ2PS | Converts packed signed quadwords to singles. | AVX10.1 |
| VCVTROPS2HF8 | Converts packed single-precision values to E4M3 FP8, rounding to odd, which avoids double-rounding errors when the result is narrowed again. | AVX10_V2_AUX |
| VCVTROPS2HF8S | Converts packed single-precision values to E4M3 FP8, rounding to odd and saturating values too large for FP8 to its largest normal. | AVX10_V2_AUX |
| VCVTSD2SH | Converts the low double of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTSD2SS | Converts the low double of the second source to single, rounding as MXCSR or the instruction selects; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SD | Converts the low half-precision value of the second source to double, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSH2SS | Converts the low half-precision value of the second source to single, which is exact; the other elements come from the first source. | AVX10.1 |
| VCVTSH2USI | Converts the low half-precision value to an unsigned integer in a 32- or 64-bit register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTSI2SD | Converts a signed 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSI2SH | Converts a signed 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTSI2SS | Converts a signed 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSS2SD | Converts the low single of the second source to double, which is exact; the other elements come from the first source. | AVX, AVX10.1 |
| VCVTSS2SH | Converts the low single of the second source to half precision, rounding as MXCSR or the instruction selects; the rest come from the first source. | AVX10.1 |
| VCVTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX, AVX10.1 |
| VCVTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, rounding as MXCSR or the instruction selects. | AVX10.1 |
| VCVTTBF162IBS | Converts packed bfloat16 values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTBF162IUBS | Converts packed bfloat16 values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPD2DQ | Converts packed doubles to signed doublewords, truncating toward zero. | AVX, AVX10.1 |
| VCVTTPD2DQS | Converts packed doubles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2QQ | Converts packed doubles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2QQS | Converts packed doubles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UDQ | Converts packed doubles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UDQS | Converts packed doubles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPD2UQQ | Converts packed doubles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPD2UQQS | Converts packed doubles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPH2DQ | Converts packed half-precision values to signed doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2IBS | Converts packed half-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2IUBS | Converts packed half-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 16-bit element. | AVX10.2 |
| VCVTTPH2QQ | Converts packed half-precision values to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UDQ | Converts packed half-precision values to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UQQ | Converts packed half-precision values to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPH2UW | Converts packed half-precision values to unsigned words, truncating toward zero. | AVX10.1 |
| VCVTTPH2W | Converts packed half-precision values to signed words, truncating toward zero. | AVX10.1 |
| VCVTTPS2DQ | Converts packed singles to signed doublewords, truncating toward zero. | AVX, AVX10.1 |
| VCVTTPS2DQS | Converts packed singles to 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2IBS | Converts packed single-precision values to signed bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2IUBS | Converts packed single-precision values to unsigned bytes, truncating and saturating, each result in the low byte of a zeroed 32-bit element. | AVX10.2 |
| VCVTTPS2QQ | Converts packed singles to signed quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2QQS | Converts packed singles to 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UDQ | Converts packed singles to unsigned doublewords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UDQS | Converts packed singles to unsigned 32-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTPS2UQQ | Converts packed singles to unsigned quadwords, truncating toward zero. | AVX10.1 |
| VCVTTPS2UQQS | Converts packed singles to unsigned 64-bit integers with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2SI | Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX, AVX10.1 |
| VCVTTSD2SIS | Converts the low double to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSD2USI | Converts the low double to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSD2USIS | Converts the low double to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSH2SI | Converts the low half-precision value to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSH2USI | Converts the low half-precision value to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2SI | Converts the low single to a signed 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX, AVX10.1 |
| VCVTTSS2SIS | Converts the low single to a signed 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTTSS2USI | Converts the low single to an unsigned 32- or 64-bit integer in a general-purpose register, truncating toward zero. | AVX10.1 |
| VCVTTSS2USIS | Converts the low single to an unsigned 32- or 64-bit integer with truncation and, if the invalid exception is masked, saturation and zero for NaN. | AVX10.2 |
| VCVTUDQ2PD | Converts packed unsigned doublewords to doubles. | AVX10.1 |
| VCVTUDQ2PH | Converts packed unsigned doublewords to half precision. | AVX10.1 |
| VCVTUDQ2PS | Converts packed unsigned doublewords to singles. | AVX10.1 |
| VCVTUQQ2PD | Converts packed unsigned quadwords to doubles. | AVX10.1 |
| VCVTUQQ2PH | Converts packed unsigned quadwords to half precision. | AVX10.1 |
| VCVTUQQ2PS | Converts packed unsigned quadwords to singles. | AVX10.1 |
| VCVTUSI2SD | Converts an unsigned 32- or 64-bit integer to double in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SH | Converts an unsigned 32- or 64-bit integer to half precision in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUSI2SS | Converts an unsigned 32- or 64-bit integer to single in the low element; the other elements come from the first source. | AVX10.1 |
| VCVTUW2PH | Converts packed unsigned words to half precision. | AVX10.1 |
| VCVTW2PH | Converts packed signed words to half precision. | AVX10.1 |
| VDBPSADBW | Sums absolute differences of 4-byte groups of the two sources into 16-bit results, after an immediate shuffles the second within each 128-bit lane. | AVX10.1 |
| VDIVBF16 | Divides packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VDIVPD | Divides packed doubles. | AVX, AVX10.1 |
| VDIVPH | Divides packed half-precision values. | AVX10.1 |
| VDIVPS | Divides packed singles. | AVX, AVX10.1 |
| VDIVSD | Divides the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VDIVSH | Divides the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VDIVSS | Divides the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VDPBF16PS | Multiplies pairs of bfloat16 values and adds both products to the matching single-precision accumulator. | AVX10.1 |
| VDPPD | Computes a dot product of two packed doubles, with an immediate choosing which products to add and where the sum goes. | AVX |
| VDPPHPS | Multiplies pairs of half-precision values and adds both products to the matching single-precision accumulator. | AVX10.2 |
| VDPPS | Computes a dot product of the singles in each 128-bit lane, with an immediate choosing which products to add and where the sums go. | AVX |
| VERR | Sets ZF if the segment that a selector names can be read at this privilege level, without loading it. | System |
| VERW | Sets ZF if the segment that a selector names can be written at this privilege level, without loading it. | System |
| VEXP2PD | Approximates 2 to the power of each packed double of a ZMM register, with a relative error below 2^-23. | AVX512ER |
| VEXP2PS | Approximates 2 to the power of each packed single of a ZMM register, with a relative error below 2^-23. | AVX512ER |
| VEXPANDPD | Spreads consecutive doubles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXPANDPS | Spreads consecutive singles from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VEXTRACTF128 | Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory. | AVX |
| VEXTRACTF32X4 | Copies the 128-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF32X8 | Copies the 256-bit block of singles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X2 | Copies the 128-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTF64X4 | Copies the 256-bit block of doubles that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI128 | Copies the 128-bit half of a YMM register that an immediate selects to an XMM register or memory; AVX2. | AVX2 |
| VEXTRACTI32X4 | Copies the 128-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI32X8 | Copies the 256-bit block of doublewords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X2 | Copies the 128-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTI64X4 | Copies the 256-bit block of quadwords that an immediate selects to a register or memory, masked per element. | AVX10.1 |
| VEXTRACTPS | Copies the single that an immediate selects from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VFCMADDCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source and adds the products to the destination. | AVX10.1 |
| VFCMADDCSH | Multiplies the low complex half-precision number of the first source by the conjugate of the second's and adds the product to the destination. | AVX10.1 |
| VFCMULCPH | Multiplies packed complex half-precision numbers by the complex conjugates of the second source. | AVX10.1 |
| VFCMULCSH | Multiplies the low complex half-precision number of the first source by the complex conjugate of the second source's. | AVX10.1 |
| VFIXUPIMMPD | Replaces special doubles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMPS | Replaces special singles (such as NaN) of the first source with responses from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSD | Replaces a special low double (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFIXUPIMMSS | Replaces a special low single (such as NaN) of the first source with a response from a table in the second; an immediate controls exceptions. | AVX10.1 |
| VFMADD132BF16 | Fused multiply-add of packed bfloat16 values: first operand times third plus second, into the first. | AVX10.2 |
| VFMADD132PD | Fused multiply-add of packed doubles: first operand times third plus second, into the first. | FMA, AVX10.1 |
| VFMADD132PH | Fused multiply-add of packed half-precision values: first operand times third plus second, into the first. | AVX10.1 |
| VFMADD132PS | Fused multiply-add of packed singles: first operand times third plus second, into the first. | FMA, AVX10.1 |
| VFMADD132SD | Fused multiply-add of the low doubles: first times third plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD132SH | Fused multiply-add of the low half-precision values: first times third plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD132SS | Fused multiply-add of the low singles: first times third plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD213BF16 | Fused multiply-add of packed bfloat16 values: second operand times first plus third, into the first. | AVX10.2 |
| VFMADD213PD | Fused multiply-add of packed doubles: second operand times first plus third, into the first. | FMA, AVX10.1 |
| VFMADD213PH | Fused multiply-add of packed half-precision values: second operand times first plus third, into the first. | AVX10.1 |
| VFMADD213PS | Fused multiply-add of packed singles: second operand times first plus third, into the first. | FMA, AVX10.1 |
| VFMADD213SD | Fused multiply-add of the low doubles: second times first plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD213SH | Fused multiply-add of the low half-precision values: second times first plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD213SS | Fused multiply-add of the low singles: second times first plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD231BF16 | Fused multiply-add of packed bfloat16 values: second operand times third plus first, into the first. | AVX10.2 |
| VFMADD231PD | Fused multiply-add of packed doubles: second operand times third plus first, into the first. | FMA, AVX10.1 |
| VFMADD231PH | Fused multiply-add of packed half-precision values: second operand times third plus first, into the first. | AVX10.1 |
| VFMADD231PS | Fused multiply-add of packed singles: second operand times third plus first, into the first. | FMA, AVX10.1 |
| VFMADD231SD | Fused multiply-add of the low doubles: second times third plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADD231SH | Fused multiply-add of the low half-precision values: second times third plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMADD231SS | Fused multiply-add of the low singles: second times third plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMADDCPH | Multiplies packed complex numbers, each a pair of half-precision values, and adds the products to the destination. | AVX10.1 |
| VFMADDCSH | Multiplies the low complex numbers, each a pair of half-precision values, and adds the product to the destination. | AVX10.1 |
| VFMADDPD | Multiplies packed doubles and adds a third operand, rounding once, with a separate destination (four operands); FMA4. | FMA4 |
| VFMADDPS | Multiplies packed singles and adds a third operand, rounding once, with a separate destination (four operands); FMA4. | FMA4 |
| VFMADDSD | Multiplies the low doubles of two operands and adds a third, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMADDSS | Multiplies the low singles of two operands and adds a third, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMADDSUB132PD | Fused multiply of packed doubles, first times third, minus the second in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB132PH | Fused multiply of packed half-precision values, first times third, minus the second in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB132PS | Fused multiply of packed singles, first times third, minus the second in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB213PD | Fused multiply of packed doubles, second times first, minus the third in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB213PH | Fused multiply of packed half-precision values, second times first, minus the third in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB213PS | Fused multiply of packed singles, second times first, minus the third in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB231PD | Fused multiply of packed doubles, second times third, minus the first in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUB231PH | Fused multiply of packed half-precision values, second times third, minus the first in even elements and plus it in odd ones, into the first. | AVX10.1 |
| VFMADDSUB231PS | Fused multiply of packed singles, second times third, minus the first in even elements and plus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMADDSUBPD | Multiplies packed doubles and subtracts the third operand in even and adds it in odd elements, rounding once; FMA4. | FMA4 |
| VFMADDSUBPS | Multiplies packed singles and subtracts the third operand in even and adds it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUB132BF16 | Fused multiply-subtract of packed bfloat16 values: first operand times third minus second, into the first. | AVX10.2 |
| VFMSUB132PD | Fused multiply-subtract of packed doubles: first operand times third minus second, into the first. | FMA, AVX10.1 |
| VFMSUB132PH | Fused multiply-subtract of packed half-precision values: first operand times third minus second, into the first. | AVX10.1 |
| VFMSUB132PS | Fused multiply-subtract of packed singles: first operand times third minus second, into the first. | FMA, AVX10.1 |
| VFMSUB132SD | Fused multiply-subtract of the low doubles: first times third minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB132SH | Fused multiply-subtract of the low half-precision values: first times third minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB132SS | Fused multiply-subtract of the low singles: first times third minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB213BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times first minus third, into the first. | AVX10.2 |
| VFMSUB213PD | Fused multiply-subtract of packed doubles: second operand times first minus third, into the first. | FMA, AVX10.1 |
| VFMSUB213PH | Fused multiply-subtract of packed half-precision values: second operand times first minus third, into the first. | AVX10.1 |
| VFMSUB213PS | Fused multiply-subtract of packed singles: second operand times first minus third, into the first. | FMA, AVX10.1 |
| VFMSUB213SD | Fused multiply-subtract of the low doubles: second times first minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB213SH | Fused multiply-subtract of the low half-precision values: second times first minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB213SS | Fused multiply-subtract of the low singles: second times first minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB231BF16 | Fused multiply-subtract of packed bfloat16 values: second operand times third minus first, into the first. | AVX10.2 |
| VFMSUB231PD | Fused multiply-subtract of packed doubles: second operand times third minus first, into the first. | FMA, AVX10.1 |
| VFMSUB231PH | Fused multiply-subtract of packed half-precision values: second operand times third minus first, into the first. | AVX10.1 |
| VFMSUB231PS | Fused multiply-subtract of packed singles: second operand times third minus first, into the first. | FMA, AVX10.1 |
| VFMSUB231SD | Fused multiply-subtract of the low doubles: second times third minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUB231SH | Fused multiply-subtract of the low half-precision values: second times third minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFMSUB231SS | Fused multiply-subtract of the low singles: second times third minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFMSUBADD132PD | Fused multiply of packed doubles, first times third, plus the second in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD132PH | Fused multiply of packed half-precision values, first times third, plus the second in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD132PS | Fused multiply of packed singles, first times third, plus the second in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD213PD | Fused multiply of packed doubles, second times first, plus the third in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD213PH | Fused multiply of packed half-precision values, second times first, plus the third in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD213PS | Fused multiply of packed singles, second times first, plus the third in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD231PD | Fused multiply of packed doubles, second times third, plus the first in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADD231PH | Fused multiply of packed half-precision values, second times third, plus the first in even elements and minus it in odd ones, into the first. | AVX10.1 |
| VFMSUBADD231PS | Fused multiply of packed singles, second times third, plus the first in even elements and minus it in odd ones, into the first. | FMA, AVX10.1 |
| VFMSUBADDPD | Multiplies packed doubles and adds the third operand in even and subtracts it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUBADDPS | Multiplies packed singles and adds the third operand in even and subtracts it in odd elements, rounding once; FMA4. | FMA4 |
| VFMSUBPD | Multiplies packed doubles and subtracts a third operand, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMSUBPS | Multiplies packed singles and subtracts a third operand, rounding once, into a separate destination; FMA4. | FMA4 |
| VFMSUBSD | Multiplies the low doubles of two operands and subtracts a third, rounding once; FMA4. | FMA4 |
| VFMSUBSS | Multiplies the low singles of two operands and subtracts a third, rounding once; FMA4. | FMA4 |
| VFMULCPH | Multiplies packed complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFMULCSH | Multiplies the low complex numbers, each a pair of half-precision values. | AVX10.1 |
| VFNMADD132BF16 | Fused negated multiply-add of packed bfloat16 values: minus first operand times third, plus second, into the first. | AVX10.2 |
| VFNMADD132PD | Fused negated multiply-add of packed doubles: minus first operand times third, plus second, into the first. | FMA, AVX10.1 |
| VFNMADD132PH | Fused negated multiply-add of packed half-precision values: minus first operand times third, plus second, into the first. | AVX10.1 |
| VFNMADD132PS | Fused negated multiply-add of packed singles: minus first operand times third, plus second, into the first. | FMA, AVX10.1 |
| VFNMADD132SD | Fused negated multiply-add of the low doubles: minus first times third, plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD132SH | Fused negated multiply-add of the low half-precision values: minus first times third, plus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD132SS | Fused negated multiply-add of the low singles: minus first times third, plus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD213BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times first, plus third, into the first. | AVX10.2 |
| VFNMADD213PD | Fused negated multiply-add of packed doubles: minus second operand times first, plus third, into the first. | FMA, AVX10.1 |
| VFNMADD213PH | Fused negated multiply-add of packed half-precision values: minus second operand times first, plus third, into the first. | AVX10.1 |
| VFNMADD213PS | Fused negated multiply-add of packed singles: minus second operand times first, plus third, into the first. | FMA, AVX10.1 |
| VFNMADD213SD | Fused negated multiply-add of the low doubles: minus second times first, plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD213SH | Fused negated multiply-add of the low half-precision values: minus second times first, plus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD213SS | Fused negated multiply-add of the low singles: minus second times first, plus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD231BF16 | Fused negated multiply-add of packed bfloat16 values: minus second operand times third, plus first, into the first. | AVX10.2 |
| VFNMADD231PD | Fused negated multiply-add of packed doubles: minus second operand times third, plus first, into the first. | FMA, AVX10.1 |
| VFNMADD231PH | Fused negated multiply-add of packed half-precision values: minus second operand times third, plus first, into the first. | AVX10.1 |
| VFNMADD231PS | Fused negated multiply-add of packed singles: minus second operand times third, plus first, into the first. | FMA, AVX10.1 |
| VFNMADD231SD | Fused negated multiply-add of the low doubles: minus second times third, plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADD231SH | Fused negated multiply-add of the low half-precision values: minus second times third, plus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMADD231SS | Fused negated multiply-add of the low singles: minus second times third, plus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMADDPD | Negates the products of packed doubles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDPS | Negates the products of packed singles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDSD | Negates the product of the low doubles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMADDSS | Negates the product of the low singles and adds a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUB132BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus first operand times third, minus second, into the first. | AVX10.2 |
| VFNMSUB132PD | Fused negated multiply-subtract of packed doubles: minus first operand times third, minus second, into the first. | FMA, AVX10.1 |
| VFNMSUB132PH | Fused negated multiply-subtract of packed half-precision values: minus first operand times third, minus second, into the first. | AVX10.1 |
| VFNMSUB132PS | Fused negated multiply-subtract of packed singles: minus first operand times third, minus second, into the first. | FMA, AVX10.1 |
| VFNMSUB132SD | Fused negated multiply-subtract of the low doubles: minus first times third, minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB132SH | Fused negated multiply-subtract of the low half-precision values: minus first times third, minus second, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB132SS | Fused negated multiply-subtract of the low singles: minus first times third, minus second, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB213BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times first, minus third, into the first. | AVX10.2 |
| VFNMSUB213PD | Fused negated multiply-subtract of packed doubles: minus second operand times first, minus third, into the first. | FMA, AVX10.1 |
| VFNMSUB213PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times first, minus third, into the first. | AVX10.1 |
| VFNMSUB213PS | Fused negated multiply-subtract of packed singles: minus second operand times first, minus third, into the first. | FMA, AVX10.1 |
| VFNMSUB213SD | Fused negated multiply-subtract of the low doubles: minus second times first, minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB213SH | Fused negated multiply-subtract of the low half-precision values: minus second times first, minus third, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB213SS | Fused negated multiply-subtract of the low singles: minus second times first, minus third, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB231BF16 | Fused negated multiply-subtract of packed bfloat16 values: minus second operand times third, minus first, into the first. | AVX10.2 |
| VFNMSUB231PD | Fused negated multiply-subtract of packed doubles: minus second operand times third, minus first, into the first. | FMA, AVX10.1 |
| VFNMSUB231PH | Fused negated multiply-subtract of packed half-precision values: minus second operand times third, minus first, into the first. | AVX10.1 |
| VFNMSUB231PS | Fused negated multiply-subtract of packed singles: minus second operand times third, minus first, into the first. | FMA, AVX10.1 |
| VFNMSUB231SD | Fused negated multiply-subtract of the low doubles: minus second times third, minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUB231SH | Fused negated multiply-subtract of the low half-precision values: minus second times third, minus first, into the first; the rest is unchanged. | AVX10.1 |
| VFNMSUB231SS | Fused negated multiply-subtract of the low singles: minus second times third, minus first, into the first; the rest is unchanged. | FMA, AVX10.1 |
| VFNMSUBPD | Negates the products of packed doubles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBPS | Negates the products of packed singles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBSD | Negates the product of the low doubles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFNMSUBSS | Negates the product of the low singles and subtracts a third operand, rounding once; FMA4. | FMA4 |
| VFPCLASSBF16 | Tests packed bfloat16 values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.2 |
| VFPCLASSPD | Tests packed doubles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPH | Tests packed half-precision values for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSPS | Tests packed singles for the classes an immediate selects, such as NaN, zero or infinity, and writes the results to a mask register. | AVX10.1 |
| VFPCLASSSD | Tests the low double for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSH | Tests the low half-precision value for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFPCLASSSS | Tests the low single for the classes an immediate selects, such as NaN, zero or infinity, and writes the result to a mask register. | AVX10.1 |
| VFRCZPD | Extracts the fractional part of each packed double of an XMM or YMM operand, exactly; XOP. | XOP |
| VFRCZPS | Extracts the fractional part of each packed single of an XMM or YMM operand, exactly; XOP. | XOP |
| VFRCZSD | Extracts the fractional part of the low double of an XMM register or memory, exactly; XOP. | XOP |
| VFRCZSS | Extracts the fractional part of the low single of an XMM register or memory, exactly; XOP. | XOP |
| VGATHERDPD | Loads doubles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERDPS | Loads singles from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERPF0DPD | Prefetches the doubles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0DPS | Prefetches the singles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0QPD | Prefetches the doubles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF0QPS | Prefetches the singles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VGATHERPF1DPD | Prefetches the doubles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1DPS | Prefetches the singles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1QPD | Prefetches the doubles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERPF1QPS | Prefetches the singles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VGATHERQPD | Loads doubles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGATHERQPS | Loads singles from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VGETEXPBF16 | Extracts the unbiased exponent of each packed bfloat16 value as a bfloat16 number. | AVX10.2 |
| VGETEXPPD | Extracts the unbiased exponent of packed doubles as floating-point numbers. | AVX10.1 |
| VGETEXPPH | Extracts the unbiased exponent of packed half-precision values as floating-point numbers. | AVX10.1 |
| VGETEXPPS | Extracts the unbiased exponent of packed singles as floating-point numbers. | AVX10.1 |
| VGETEXPSD | Extracts the unbiased exponent of the low double of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETEXPSH | Extracts the unbiased exponent of the low half-precision value of the second source as a float; the other elements come from the first source. | AVX10.1 |
| VGETEXPSS | Extracts the unbiased exponent of the low single of the second source as a floating-point number; the other elements come from the first source. | AVX10.1 |
| VGETMANTBF16 | Extracts the normalized mantissa of each packed bfloat16 value, with the interval and sign handling chosen by an immediate. | AVX10.2 |
| VGETMANTPD | Extracts the normalized mantissa of packed doubles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPH | Extracts the normalized mantissa of packed half-precision values, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTPS | Extracts the normalized mantissa of packed singles, with the interval and sign handling chosen by an immediate. | AVX10.1 |
| VGETMANTSD | Extracts the normalized mantissa of the low double of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGETMANTSH | Extracts the normalized mantissa of the low half-precision value of the second source, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VGETMANTSS | Extracts the normalized mantissa of the low single of the second source, as an immediate selects; the other elements come from the first source. | AVX10.1 |
| VGF2P8AFFINEINVQB | Replaces each byte with its inverse in GF(2^8), then applies an affine transformation given by an 8x8 bit matrix and an immediate constant. | GFNI, AVX10.1 |
| VGF2P8AFFINEQB | Applies an affine transformation to each byte, given by an 8x8 bit matrix from the second source and an immediate constant. | GFNI, AVX10.1 |
| VGF2P8MULB | Multiplies bytes in the finite field GF(2^8) defined by the AES polynomial x^8 + x^4 + x^3 + x + 1. | GFNI, AVX10.1 |
| VHADDPD | Adds the pair of doubles within each 128-bit lane of two sources, the first source's sums going to the even positions. | AVX |
| VHADDPS | Adds adjacent pairs of singles within each 128-bit lane of two sources, the first source's two sums going low in the lane. | AVX |
| VHSUBPD | Subtracts the high double from the low one within each 128-bit lane of two sources, the first source's results going to the even positions. | AVX |
| VHSUBPS | Subtracts the odd single from the even one in adjacent pairs within each 128-bit lane, the first source's results going low. | AVX |
| VINSERTF128 | Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits from an XMM register or memory. | AVX |
| VINSERTF32X4 | Replaces the 128-bit block that an immediate selects with four singles from a register or memory. | AVX10.1 |
| VINSERTF32X8 | Replaces the 256-bit block that an immediate selects with eight singles from a register or memory. | AVX10.1 |
| VINSERTF64X2 | Replaces the 128-bit block that an immediate selects with two doubles from a register or memory. | AVX10.1 |
| VINSERTF64X4 | Replaces the 256-bit block that an immediate selects with four doubles from a register or memory. | AVX10.1 |
| VINSERTI128 | Copies the first source to a YMM register and replaces the half an immediate selects with 128 bits of an XMM register or memory; AVX2. | AVX2 |
| VINSERTI32X4 | Replaces the 128-bit block that an immediate selects with four doublewords from a register or memory. | AVX10.1 |
| VINSERTI32X8 | Replaces the 256-bit block that an immediate selects with eight doublewords from a register or memory. | AVX10.1 |
| VINSERTI64X2 | Replaces the 128-bit block that an immediate selects with two quadwords from a register or memory. | AVX10.1 |
| VINSERTI64X4 | Replaces the 256-bit block that an immediate selects with four quadwords from a register or memory. | AVX10.1 |
| VINSERTPS | Inserts a single from a register or memory into an XMM register at the position an immediate gives, and can zero other elements. | AVX, AVX10.1 |
| VLDDQU | Loads 128 or 256 unaligned bits like VMOVDQU, but may read more bytes around them, for loads that cross cache lines. | AVX |
| VLDMXCSR | Loads the MXCSR register, the SSE control and status bits, from memory; the VEX form of LDMXCSR. | AVX |
| VMASKMOVDQU | Stores the bytes of an XMM register whose mask byte has its top bit set to [RDI], non-temporally; the VEX form of MASKMOVDQU. | AVX |
| VMASKMOVPD | Loads or stores packed doubles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX |
| VMASKMOVPS | Loads or stores packed singles only where the sign bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX |
| VMAXBF16 | Returns the larger of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMAXPD | Returns the larger of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMAXPH | Returns the larger of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMAXPS | Returns the larger of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMAXSD | Returns the larger of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMAXSH | Returns the larger low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMAXSS | Returns the larger of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMCALL | Causes a VM exit from a guest to its hypervisor, which defines what the call means. | VMX |
| VMCLEAR | Writes the data of the VMCS at a physical address back to its memory region and sets its launch state to clear. | VMX |
| VMFUNC | Invokes the VM function that EAX selects, such as EPTP switching (0), from a guest without a VM exit. | VMX |
| VMINBF16 | Returns the smaller of each pair of packed bfloat16 values, with the x86 convention of returning the second operand if either is NaN or both are zero. | AVX10.2 |
| VMINMAXBF16 | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed bfloat16 values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXPS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSD | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low doubles, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSH | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low half-precision values, as an immediate selects, with sign control. | AVX10.2 |
| VMINMAXSS | Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low singles, as an immediate selects, with sign control. | AVX10.2 |
| VMINPD | Returns the smaller of each pair of packed doubles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMINPH | Returns the smaller of each pair of packed half-precision values, or the second operand if either is NaN or both are zero. | AVX10.1 |
| VMINPS | Returns the smaller of each pair of packed singles, or the second operand if either is NaN or both are zero. | AVX, AVX10.1 |
| VMINSD | Returns the smaller of the low doubles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMINSH | Returns the smaller low half-precision value, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX10.1 |
| VMINSS | Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source. | AVX, AVX10.1 |
| VMLAUNCH | Enters the guest that the current VMCS describes, for a VMCS whose launch state is clear, and marks the VMCS launched. | VMX |
| VMLOAD | Loads the processor state that VMRUN does not load (segment and system registers) from the VMCB at the address in rAX; AMD SVM. | SVM |
| VMMCALL | Exits from a guest to its hypervisor with a VM exit, for a call whose meaning the hypervisor defines; AMD SVM. | SVM |
| VMOVAPD | Moves packed doubles between registers and memory that must be aligned to the vector size. | AVX, AVX10.1 |
| VMOVAPS | Moves packed singles between registers and memory that must be aligned to the vector size. | AVX, AVX10.1 |
| VMOVD | Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX, AVX10.1, AVX10.2 |
| VMOVDDUP | Duplicates each even-numbered double into the next odd position. | AVX, AVX10.1 |
| VMOVDQA | Moves 128 or 256 bits of integer data between vector registers and memory, which must be aligned to the vector size. | AVX |
| VMOVDQA32 | Moves integer vectors between registers and aligned memory, masked at doubleword granularity. | AVX10.1 |
| VMOVDQA64 | Moves integer vectors between registers and aligned memory, masked at quadword granularity. | AVX10.1 |
| VMOVDQU | Moves 128 or 256 bits of integer data between vector registers and memory without an alignment requirement. | AVX |
| VMOVDQU16 | Moves integer vectors between registers and memory without an alignment requirement, masked at word granularity. | AVX10.1 |
| VMOVDQU32 | Moves integer vectors between registers and memory without an alignment requirement, masked at doubleword granularity. | AVX10.1 |
| VMOVDQU64 | Moves integer vectors between registers and memory without an alignment requirement, masked at quadword granularity. | AVX10.1 |
| VMOVDQU8 | Moves integer vectors between registers and memory without an alignment requirement, masked at byte granularity. | AVX10.1 |
| VMOVHLPS | Moves the high two singles of the second source into the low half of the result, the high half coming from the first source. | AVX, AVX10.1 |
| VMOVHPD | Loads a double from memory into the high half of an XMM register, or stores the high double to memory. | AVX, AVX10.1 |
| VMOVHPS | Loads two singles from memory into the high half of an XMM register, or stores the high two to memory. | AVX, AVX10.1 |
| VMOVLHPS | Moves the low two singles of the second source into the high half of the result, the low half coming from the first source. | AVX, AVX10.1 |
| VMOVLPD | Loads a double from memory into the low half of an XMM register, or stores the low double to memory. | AVX, AVX10.1 |
| VMOVLPS | Loads two singles from memory into the low half of an XMM register, or stores the low two to memory. | AVX, AVX10.1 |
| VMOVMSKPD | Copies the sign bits of the packed doubles of an XMM or YMM register into the low bits of a general-purpose register. | AVX |
| VMOVMSKPS | Copies the sign bits of the packed singles of an XMM or YMM register into the low bits of a general-purpose register. | AVX |
| VMOVNTDQ | Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVNTDQA | Loads a vector from aligned memory with a non-temporal hint, which lets it read write-combining memory efficiently. | AVX, AVX2, AVX10.1 |
| VMOVNTPD | Stores packed doubles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVNTPS | Stores packed singles to aligned memory with a non-temporal hint that avoids polluting the caches. | AVX, AVX10.1 |
| VMOVQ | Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination. | AVX, AVX10.1 |
| VMOVRSB | Loads a vector of bytes under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSD | Loads a vector of doublewords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSQ | Loads a vector of quadwords under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVRSW | Loads a vector of words under a write mask, with a hint that other cores are likely to read the same data before it is written. | MOVRS |
| VMOVSD | Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX, AVX10.1 |
| VMOVSH | Moves the low half-precision value between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX10.1 |
| VMOVSHDUP | Duplicates each odd-numbered single into the even position below it. | AVX, AVX10.1 |
| VMOVSLDUP | Duplicates each even-numbered single into the odd position above it. | AVX, AVX10.1 |
| VMOVSS | Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register. | AVX, AVX10.1 |
| VMOVUPD | Moves packed doubles between registers and memory without an alignment requirement. | AVX, AVX10.1 |
| VMOVUPS | Moves packed singles between registers and memory without an alignment requirement. | AVX, AVX10.1 |
| VMOVW | Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form. | AVX10.1, AVX10.2 |
| VMPSADBW | Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first. | AVX, AVX2, AVX10.2 |
| VMPTRLD | Makes the VMCS at the physical address in a 64-bit memory operand the current VMCS. | VMX |
| VMPTRST | Stores the physical address of the current VMCS to a 64-bit memory operand. | VMX |
| VMREAD | Reads the field of the current VMCS whose encoding a register gives into a register or memory. | VMX |
| VMRESUME | Enters the guest that the current VMCS describes again, for a VMCS that VMLAUNCH has launched. | VMX |
| VMRUN | Runs the guest that the virtual machine control block (VMCB) at the physical address in rAX describes; AMD SVM. | SVM |
| VMSAVE | Saves the processor state that VMRUN does not save to the VMCB at the physical address in rAX; AMD SVM. | SVM |
| VMULBF16 | Multiplies packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VMULPD | Multiplies packed doubles. | AVX, AVX10.1 |
| VMULPH | Multiplies packed half-precision values. | AVX10.1 |
| VMULPS | Multiplies packed singles. | AVX, AVX10.1 |
| VMULSD | Multiplies the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VMULSH | Multiplies the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VMULSS | Multiplies the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VMWRITE | Writes a register or memory operand to the field of the current VMCS whose encoding another register gives. | VMX |
| VMXOFF | Takes the processor out of VMX operation and unblocks INIT signals again. | VMX |
| VMXON | Puts the processor in VMX operation, taking the physical address of a 4-KByte VMXON region from a 64-bit memory operand. | VMX |
| VORPD | Computes the bitwise OR of packed doubles. | AVX, AVX10.1 |
| VORPS | Computes the bitwise OR of packed singles. | AVX, AVX10.1 |
| VP2INTERSECTD | Compares every doubleword of one vector with every one of another and marks the elements that have a match in a pair of mask registers. | AVX512-VP2INTERSECT |
| VP2INTERSECTQ | Compares every quadword of one vector with every one of another and marks the elements that have a match in a pair of mask registers. | AVX512-VP2INTERSECT |
| VP4DPWSSD | Adds four dot products of signed word pairs in a row to doublewords, with four consecutive ZMM registers and memory. | AVX512_4VNNIW |
| VP4DPWSSDS | Adds four dot products of signed word pairs in a row to doublewords with signed saturation, with four consecutive ZMM registers and memory. | AVX512_4VNNIW |
| VPABSB | Computes the absolute value of packed signed bytes. | AVX, AVX2, AVX10.1 |
| VPABSD | Computes the absolute value of packed signed doublewords. | AVX, AVX2, AVX10.1 |
| VPABSQ | Computes the absolute value of packed signed quadwords. | AVX10.1 |
| VPABSW | Computes the absolute value of packed signed words. | AVX, AVX2, AVX10.1 |
| VPACKSSDW | Narrows signed doublewords from two sources to words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPACKSSWB | Narrows signed words from two sources to bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPACKUSDW | Narrows signed doublewords from two sources to words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPACKUSWB | Narrows signed words from two sources to bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDB | Adds packed bytes, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDD | Adds packed doublewords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDQ | Adds packed quadwords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPADDSB | Adds packed signed bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPADDSW | Adds packed signed words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPADDUSB | Adds packed unsigned bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDUSW | Adds packed unsigned words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPADDW | Adds packed words, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPALIGNR | Concatenates two sources in each 128-bit lane and extracts 16 bytes starting at a byte offset given by an immediate. | AVX, AVX2, AVX10.1 |
| VPAND | Computes the bitwise AND of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPANDD | Computes the bitwise AND of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPANDN | Computes the bitwise AND of the inverted first source with the second, in XMM or YMM registers (YMM with AVX2). | AVX, AVX2 |
| VPANDND | Computes the bitwise AND of the inverted first source with the second, masked at doubleword granularity. | AVX10.1 |
| VPANDNQ | Computes the bitwise AND of the inverted first source with the second, masked at quadword granularity. | AVX10.1 |
| VPANDQ | Computes the bitwise AND of two vectors, masked at quadword granularity. | AVX10.1 |
| VPAVGB | Computes the rounded average of packed unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPAVGW | Computes the rounded average of packed unsigned words. | AVX, AVX2, AVX10.1 |
| VPBLENDD | Picks each doubleword from the first or the second source, as a bit of an immediate says; AVX2. | AVX2 |
| VPBLENDMB | Picks each byte from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMD | Picks each doubleword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMQ | Picks each quadword from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDMW | Picks each word from the second source where a mask bit is set, otherwise from the first. | AVX10.1 |
| VPBLENDVB | Picks each byte from the first or the second source by the top bit of the matching byte of a fourth register operand. | AVX, AVX2 |
| VPBLENDW | Picks each word from the first or the second source by a bit of an immediate, the same eight bits for each 128-bit lane. | AVX, AVX2 |
| VPBROADCASTB | Copies one byte from a register or memory to every byte of a vector. | AVX2, AVX10.1 |
| VPBROADCASTD | Copies one doubleword from a register or memory to every doubleword of a vector. | AVX2, AVX10.1 |
| VPBROADCASTMB2Q | Copies the low 8 bits of a mask register, zero-extended, to every quadword. | AVX10.1 |
| VPBROADCASTMW2D | Copies the low 16 bits of a mask register, zero-extended, to every doubleword. | AVX10.1 |
| VPBROADCASTQ | Copies one quadword from a register or memory to every quadword of a vector. | AVX2, AVX10.1 |
| VPBROADCASTW | Copies one word from a register or memory to every word of a vector. | AVX2, AVX10.1 |
| VPCLMULQDQ | Carry-less multiplies one quadword of each source, chosen by an immediate, into a 128-bit product in each 128-bit lane. | AVX, VPCLMULQDQ, AVX10.1 |
| VPCMOV | Takes each bit from the first or the second source as the matching bit of a third source is set or clear; XOP. | XOP |
| VPCMPB | Compares packed signed bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPD | Compares packed signed doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPEQB | Compares packed bytes for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQD | Compares packed doublewords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQQ | Compares packed quadwords for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPEQW | Compares packed words for equality; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPESTRI | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning an index in ECX. | AVX |
| VPCMPESTRM | Compares two strings of explicit lengths in EAX and EDX (RAX and RDX with VEX.W1) as an immediate says, returning a mask in XMM0. | AVX |
| VPCMPGTB | Tests packed signed bytes for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTD | Tests packed signed doublewords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTQ | Tests packed signed quadwords for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPGTW | Tests packed signed words for greater than; the VEX form writes all-ones or zero elements, the EVEX form a mask register. | AVX, AVX2, AVX10.1 |
| VPCMPISTRI | Compares two zero-terminated strings in XMM registers as an immediate says, returning an index in ECX; VEX form. | AVX |
| VPCMPISTRM | Compares two zero-terminated strings in XMM registers as an immediate says, returning a mask in XMM0; VEX form. | AVX |
| VPCMPQ | Compares packed signed quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUB | Compares packed unsigned bytes with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUD | Compares packed unsigned doublewords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUQ | Compares packed unsigned quadwords with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPUW | Compares packed unsigned words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCMPW | Compares packed signed words with a predicate chosen by an immediate and writes the results to a mask register. | AVX10.1 |
| VPCOMB | Compares packed signed bytes by the predicate an immediate selects, such as less than (VPCOMLTB), into all-ones or all-zeros bytes; XOP. | XOP |
| VPCOMD | Compares packed signed doublewords by the predicate an immediate selects, into all-ones or all-zeros doublewords; XOP. | XOP |
| VPCOMPRESSB | Packs the bytes selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSD | Packs the doublewords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSQ | Packs the quadwords selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMPRESSW | Packs the words selected by a mask contiguously into the low end of a register or into memory. | AVX10.1 |
| VPCOMQ | Compares packed signed quadwords by the predicate an immediate selects, into all-ones or all-zeros quadwords; XOP. | XOP |
| VPCOMUB | Compares packed unsigned bytes by the predicate an immediate selects, into all-ones or all-zeros bytes; XOP. | XOP |
| VPCOMUD | Compares packed unsigned doublewords by the predicate an immediate selects, into all-ones or all-zeros doublewords; XOP. | XOP |
| VPCOMUQ | Compares packed unsigned quadwords by the predicate an immediate selects, into all-ones or all-zeros quadwords; XOP. | XOP |
| VPCOMUW | Compares packed unsigned words by the predicate an immediate selects, into all-ones or all-zeros words; XOP. | XOP |
| VPCOMW | Compares packed signed words by the predicate an immediate selects, into all-ones or all-zeros words; XOP. | XOP |
| VPCONFLICTD | For each doubleword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPCONFLICTQ | For each quadword, sets a bit for every lower-numbered element of the source that holds the same value. | AVX10.1 |
| VPDPBSSD | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSSDS | Multiplies signed bytes by signed bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator with signed saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUD | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBSUDS | Multiplies signed bytes of the first source by unsigned bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUSD | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPBUSDS | Multiplies unsigned bytes of the first source by signed bytes of the second and adds each group of four products to a 32-bit accumulator, saturating. | AVX-VNNI, AVX10.1 |
| VPDPBUUD | Multiplies unsigned bytes by unsigned bytes, sums each group of four products and adds the sum to the matching 32-bit accumulator. | AVX-VNNI-INT8, AVX10.2 |
| VPDPBUUDS | Multiplies unsigned bytes by unsigned bytes and adds each group of four products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT8, AVX10.2 |
| VPDPWSSD | Multiplies pairs of signed words, adds both products to the matching 32-bit accumulator. | AVX-VNNI, AVX10.1 |
| VPDPWSSDS | Multiplies pairs of signed words and adds both products to the matching 32-bit accumulator with signed saturation. | AVX-VNNI, AVX10.1 |
| VPDPWSUD | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWSUDS | Multiplies signed words of the first source by unsigned words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSD | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUSDS | Multiplies unsigned words of the first source by signed words of the second and adds each pair of products to a 32-bit accumulator, saturating. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUD | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator. | AVX-VNNI-INT16, AVX10.2 |
| VPDPWUUDS | Multiplies unsigned words by unsigned words and adds each pair of products to the matching 32-bit accumulator with unsigned saturation. | AVX-VNNI-INT16, AVX10.2 |
| VPERM2F128 | Builds each 128-bit half of a YMM result from either half of two sources, or zero, as an immediate selects. | AVX |
| VPERM2I128 | Builds each 128-bit half of a YMM result from either half of two integer sources, or zero, as an immediate selects; AVX2. | AVX2 |
| VPERMB | Rearranges the bytes of a vector across the whole register using an index vector. | AVX10.1 |
| VPERMD | Rearranges the doublewords of a vector across the whole register using an index vector. | AVX2, AVX10.1 |
| VPERMI2B | Selects bytes from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2D | Selects doublewords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PD | Selects doubles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2PS | Selects singles from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2Q | Selects quadwords from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMI2W | Selects words from two tables with an index vector that the result then overwrites. | AVX10.1 |
| VPERMIL2PD | Picks each double from either of two sources, or zero, by selectors in a third source and an immediate; XOP. | XOP |
| VPERMIL2PS | Picks each single from either of two sources, or zero, by selectors in a third source and an immediate; XOP. | XOP |
| VPERMILPD | Rearranges doubles within each 128-bit lane, controlled by an immediate or by a vector. | AVX, AVX10.1 |
| VPERMILPS | Rearranges singles within each 128-bit lane, controlled by an immediate or by a vector. | AVX, AVX10.1 |
| VPERMPD | Rearranges doubles across the whole register, controlled by an immediate or by an index vector. | AVX2, AVX10.1 |
| VPERMPS | Rearranges singles across the whole register using an index vector. | AVX2, AVX10.1 |
| VPERMQ | Rearranges quadwords across the whole register, controlled by an immediate or by an index vector. | AVX2, AVX10.1 |
| VPERMT2B | Selects bytes from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2D | Selects doublewords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PD | Selects doubles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2PS | Selects singles from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2Q | Selects quadwords from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMT2W | Selects words from two tables with an index vector, the result overwriting the first table. | AVX10.1 |
| VPERMW | Rearranges the words of a vector across the whole register using an index vector. | AVX10.1 |
| VPEXPANDB | Spreads consecutive bytes from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDD | Spreads consecutive doublewords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDQ | Spreads consecutive quadwords from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXPANDW | Spreads consecutive words from the low end of a register or from memory to the positions selected by a mask. | AVX10.1 |
| VPEXTRB | Copies the byte selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRD | Copies the doubleword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRQ | Copies the quadword selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPEXTRW | Copies the word selected by an immediate from an XMM register to a general-purpose register or memory. | AVX, AVX10.1 |
| VPGATHERDD | Loads doublewords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERDQ | Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERQD | Loads doublewords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPGATHERQQ | Loads quadwords from memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX2, AVX10.1 |
| VPHADDBD | Adds each group of four signed bytes into a signed doubleword; XOP. | XOP |
| VPHADDBQ | Adds each group of eight signed bytes into a signed quadword; XOP. | XOP |
| VPHADDBW | Adds each pair of adjacent signed bytes into a signed word; XOP. | XOP |
| VPHADDD | Adds adjacent pairs of doublewords within each 128-bit lane of two sources, the first source's sums going low in the lane. | AVX, AVX2 |
| VPHADDDQ | Adds each pair of adjacent signed doublewords into a signed quadword; XOP. | XOP |
| VPHADDSW | Adds adjacent pairs of signed words within each 128-bit lane with signed saturation, the first source's sums going low. | AVX, AVX2 |
| VPHADDUBD | Adds each group of four unsigned bytes into a doubleword; XOP. | XOP |
| VPHADDUBQ | Adds each group of eight unsigned bytes into a quadword; XOP. | XOP |
| VPHADDUBW | Adds each pair of adjacent unsigned bytes into a word; XOP. | XOP |
| VPHADDUDQ | Adds each pair of adjacent unsigned doublewords into a quadword; XOP. | XOP |
| VPHADDUWD | Adds each pair of adjacent unsigned words into a doubleword; XOP. | XOP |
| VPHADDUWQ | Adds each group of four unsigned words into a quadword; XOP. | XOP |
| VPHADDW | Adds adjacent pairs of words within each 128-bit lane of two sources, the first source's sums going low in the lane. | AVX, AVX2 |
| VPHADDWD | Adds each pair of adjacent signed words into a signed doubleword; XOP. | XOP |
| VPHADDWQ | Adds each group of four signed words into a signed quadword; XOP. | XOP |
| VPHMINPOSUW | Finds the smallest unsigned word of an XMM operand and returns it with its index in the low two words; VEX form. | AVX |
| VPHSUBBW | Subtracts the high signed byte from the low one of each word, into signed words; XOP. | XOP |
| VPHSUBD | Subtracts the odd doubleword from the even one in adjacent pairs within each 128-bit lane of two sources. | AVX, AVX2 |
| VPHSUBDQ | Subtracts the high signed doubleword from the low one of each quadword, into signed quadwords; XOP. | XOP |
| VPHSUBSW | Subtracts the odd signed word from the even one in adjacent pairs within each 128-bit lane, with signed saturation. | AVX, AVX2 |
| VPHSUBW | Subtracts the odd word from the even one in adjacent pairs within each 128-bit lane of two sources. | AVX, AVX2 |
| VPHSUBWD | Subtracts the high signed word from the low one of each doubleword, into signed doublewords; XOP. | XOP |
| VPINSRB | Inserts a byte from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRD | Inserts a doubleword from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRQ | Inserts a quadword from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPINSRW | Inserts a word from a register or memory into an XMM register at the position an immediate gives. | AVX, AVX10.1 |
| VPLZCNTD | Counts the leading zero bits of each doubleword. | AVX10.1 |
| VPLZCNTQ | Counts the leading zero bits of each quadword. | AVX10.1 |
| VPMACSDD | Multiplies packed signed doublewords and adds a third source to the products, keeping the low 32 bits without saturation; XOP. | XOP |
| VPMACSDQH | Multiplies the odd signed doublewords of two sources into quadwords and adds the quadwords of a third source; XOP. | XOP |
| VPMACSDQL | Multiplies the even signed doublewords of two sources into quadwords and adds the quadwords of a third source; XOP. | XOP |
| VPMACSSDD | Multiplies packed signed doublewords and adds a third source to the products, with signed saturation to doublewords; XOP. | XOP |
| VPMACSSDQH | Multiplies the odd signed doublewords of two sources and adds a third source's quadwords, with signed saturation; XOP. | XOP |
| VPMACSSDQL | Multiplies the even signed doublewords of two sources and adds a third source's quadwords, with signed saturation; XOP. | XOP |
| VPMACSSWD | Multiplies the odd signed words of two sources and adds a third source's doublewords, with signed saturation; XOP. | XOP |
| VPMACSSWW | Multiplies packed signed words and adds a third source's words to the products, with signed saturation; XOP. | XOP |
| VPMACSWD | Multiplies the odd signed words of two sources and adds a third source's doublewords, without saturation; XOP. | XOP |
| VPMACSWW | Multiplies packed signed words and adds a third source's words to the products, keeping the low 16 bits; XOP. | XOP |
| VPMADCSSWD | Multiplies packed signed words, adds adjacent products and a third source's doublewords, with signed saturation; XOP. | XOP |
| VPMADCSWD | Multiplies packed signed words, adds adjacent products and a third source's doublewords, without saturation; XOP. | XOP |
| VPMADD52HUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADD52LUQ | Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the low 52 bits of each product to a 64-bit accumulator. | AVX-IFMA, AVX10.1 |
| VPMADDUBSW | Multiplies unsigned bytes of the first source by signed bytes of the second and adds adjacent products into words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPMADDWD | Multiplies signed words and adds adjacent products into doublewords. | AVX, AVX2, AVX10.1 |
| VPMASKMOVD | Loads or stores packed doublewords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX2 |
| VPMASKMOVQ | Loads or stores packed quadwords only where the top bit of the matching mask element is set; in Intel's manual, masked-off elements cannot fault. | AVX2 |
| VPMAXSB | Returns the larger of each pair of signed bytes. | AVX, AVX2, AVX10.1 |
| VPMAXSD | Returns the larger of each pair of signed doublewords. | AVX, AVX2, AVX10.1 |
| VPMAXSQ | Returns the larger of each pair of signed quadwords. | AVX10.1 |
| VPMAXSW | Returns the larger of each pair of signed words. | AVX, AVX2, AVX10.1 |
| VPMAXUB | Returns the larger of each pair of unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPMAXUD | Returns the larger of each pair of unsigned doublewords. | AVX, AVX2, AVX10.1 |
| VPMAXUQ | Returns the larger of each pair of unsigned quadwords. | AVX10.1 |
| VPMAXUW | Returns the larger of each pair of unsigned words. | AVX, AVX2, AVX10.1 |
| VPMINSB | Returns the smaller of each pair of signed bytes. | AVX, AVX2, AVX10.1 |
| VPMINSD | Returns the smaller of each pair of signed doublewords. | AVX, AVX2, AVX10.1 |
| VPMINSQ | Returns the smaller of each pair of signed quadwords. | AVX10.1 |
| VPMINSW | Returns the smaller of each pair of signed words. | AVX, AVX2, AVX10.1 |
| VPMINUB | Returns the smaller of each pair of unsigned bytes. | AVX, AVX2, AVX10.1 |
| VPMINUD | Returns the smaller of each pair of unsigned doublewords. | AVX, AVX2, AVX10.1 |
| VPMINUQ | Returns the smaller of each pair of unsigned quadwords. | AVX10.1 |
| VPMINUW | Returns the smaller of each pair of unsigned words. | AVX, AVX2, AVX10.1 |
| VPMOVB2M | Sets each bit of a mask register from the sign bit of the corresponding byte. | AVX10.1 |
| VPMOVD2M | Sets each bit of a mask register from the sign bit of the corresponding doubleword. | AVX10.1 |
| VPMOVDB | Narrows packed doublewords to bytes by truncation. | AVX10.1 |
| VPMOVDW | Narrows packed doublewords to words by truncation. | AVX10.1 |
| VPMOVM2B | Sets each byte to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2D | Sets each doubleword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2Q | Sets each quadword to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVM2W | Sets each word to all ones or all zeros according to the corresponding mask bit. | AVX10.1 |
| VPMOVMSKB | Copies the top bit of each byte of an XMM or YMM register into the low bits of a general-purpose register. | AVX, AVX2 |
| VPMOVQ2M | Sets each bit of a mask register from the sign bit of the corresponding quadword. | AVX10.1 |
| VPMOVQB | Narrows packed quadwords to bytes by truncation. | AVX10.1 |
| VPMOVQD | Narrows packed quadwords to doublewords by truncation. | AVX10.1 |
| VPMOVQW | Narrows packed quadwords to words by truncation. | AVX10.1 |
| VPMOVSDB | Narrows packed signed doublewords to bytes with signed saturation. | AVX10.1 |
| VPMOVSDW | Narrows packed signed doublewords to words with signed saturation. | AVX10.1 |
| VPMOVSQB | Narrows packed signed quadwords to bytes with signed saturation. | AVX10.1 |
| VPMOVSQD | Narrows packed signed quadwords to doublewords with signed saturation. | AVX10.1 |
| VPMOVSQW | Narrows packed signed quadwords to words with signed saturation. | AVX10.1 |
| VPMOVSSDB | Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127. | AVX10_V2_AUX |
| VPMOVSWB | Narrows packed signed words to bytes with signed saturation. | AVX10.1 |
| VPMOVSXBD | Sign-extends packed bytes to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVSXBQ | Sign-extends packed bytes to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVSXBW | Sign-extends packed bytes to words. | AVX, AVX2, AVX10.1 |
| VPMOVSXDQ | Sign-extends packed doublewords to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVSXWD | Sign-extends packed words to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVSXWQ | Sign-extends packed words to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVUSDB | Narrows packed unsigned doublewords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSDW | Narrows packed unsigned doublewords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSQB | Narrows packed unsigned quadwords to bytes with unsigned saturation. | AVX10.1 |
| VPMOVUSQD | Narrows packed unsigned quadwords to doublewords with unsigned saturation. | AVX10.1 |
| VPMOVUSQW | Narrows packed unsigned quadwords to words with unsigned saturation. | AVX10.1 |
| VPMOVUSWB | Narrows packed unsigned words to bytes with unsigned saturation. | AVX10.1 |
| VPMOVW2M | Sets each bit of a mask register from the sign bit of the corresponding word. | AVX10.1 |
| VPMOVWB | Narrows packed words to bytes by truncation. | AVX10.1 |
| VPMOVZXBD | Zero-extends packed bytes to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVZXBQ | Zero-extends packed bytes to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVZXBW | Zero-extends packed bytes to words. | AVX, AVX2, AVX10.1 |
| VPMOVZXDQ | Zero-extends packed doublewords to quadwords. | AVX, AVX2, AVX10.1 |
| VPMOVZXWD | Zero-extends packed words to doublewords. | AVX, AVX2, AVX10.1 |
| VPMOVZXWQ | Zero-extends packed words to quadwords. | AVX, AVX2, AVX10.1 |
| VPMULDQ | Multiplies the signed low doublewords of each quadword into 64-bit products. | AVX, AVX2, AVX10.1 |
| VPMULHRSW | Multiplies packed signed words as Q15 fixed-point numbers, rounding each product to a Q15 result. | AVX, AVX2, AVX10.1 |
| VPMULHUW | Multiplies unsigned words and keeps the high 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULHW | Multiplies signed words and keeps the high 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULLD | Multiplies packed doublewords and keeps the low 32 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULLQ | Multiplies packed quadwords and keeps the low 64 bits of each product. | AVX10.1 |
| VPMULLW | Multiplies packed words and keeps the low 16 bits of each product. | AVX, AVX2, AVX10.1 |
| VPMULTISHIFTQB | For each byte of the result, takes 8 bits from the matching quadword of the second source at a bit offset given by a control byte of the first. | AVX10.1 |
| VPMULUDQ | Multiplies the unsigned low doublewords of each quadword into 64-bit products. | AVX, AVX2, AVX10.1 |
| VPOPCNTB | Counts the set bits in each byte. | AVX10.1 |
| VPOPCNTD | Counts the set bits in each doubleword. | AVX10.1 |
| VPOPCNTQ | Counts the set bits in each quadword. | AVX10.1 |
| VPOPCNTW | Counts the set bits in each word. | AVX10.1 |
| VPOR | Computes the bitwise OR of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPORD | Computes the bitwise OR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPORQ | Computes the bitwise OR of two vectors, masked at quadword granularity. | AVX10.1 |
| VPPERM | Picks each byte of the result from 32 bytes of two sources and optionally inverts, reverses or replaces it, by selectors in a third; XOP. | XOP |
| VPROLD | Rotates each doubleword left by an immediate count. | AVX10.1 |
| VPROLQ | Rotates each quadword left by an immediate count. | AVX10.1 |
| VPROLVD | Rotates each doubleword left by the count in the matching element of the second source. | AVX10.1 |
| VPROLVQ | Rotates each quadword left by the count in the matching element of the second source. | AVX10.1 |
| VPRORD | Rotates each doubleword right by an immediate count. | AVX10.1 |
| VPRORQ | Rotates each quadword right by an immediate count. | AVX10.1 |
| VPRORVD | Rotates each doubleword right by the count in the matching element of the second source. | AVX10.1 |
| VPRORVQ | Rotates each quadword right by the count in the matching element of the second source. | AVX10.1 |
| VPROTB | Rotates each byte left or right by a signed count from an immediate or the matching byte of a register or memory; XOP. | XOP |
| VPROTD | Rotates each doubleword left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPROTQ | Rotates each quadword left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPROTW | Rotates each word left or right by a signed count from an immediate or a register or memory; XOP. | XOP |
| VPSADBW | Sums the absolute differences of unsigned bytes over each group of eight, giving one 16-bit sum per quadword. | AVX, AVX2, AVX10.1 |
| VPSCATTERDD | Stores doublewords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERDQ | Stores quadwords to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQD | Stores doublewords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSCATTERQQ | Stores quadwords to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VPSHAB | Shifts each signed byte arithmetically left or right by the signed count in the matching byte of a second source; XOP. | XOP |
| VPSHAD | Shifts each signed doubleword arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHAQ | Shifts each signed quadword arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHAW | Shifts each signed word arithmetically left or right by a signed count per element; XOP. | XOP |
| VPSHLB | Shifts each byte logically left or right by the signed count in the matching byte of a second source; XOP. | XOP |
| VPSHLD | Shifts each doubleword logically left or right by a signed count per element; XOP. | XOP |
| VPSHLDD | Joins each doubleword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDQ | Joins each quadword of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLDVD | Joins each doubleword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVQ | Joins each quadword of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDVW | Joins each word of the destination above the matching one of the source, shifts the pair left by a per-element count and keeps the upper half. | AVX10.1 |
| VPSHLDW | Joins each word of the first source above the matching one of the second, shifts the pair left by an immediate and keeps the upper half. | AVX10.1 |
| VPSHLQ | Shifts each quadword logically left or right by a signed count per element; XOP. | XOP |
| VPSHLW | Shifts each word logically left or right by a signed count per element; XOP. | XOP |
| VPSHRDD | Joins each doubleword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDQ | Joins each quadword of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHRDVD | Joins each doubleword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVQ | Joins each quadword of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDVW | Joins each word of the source above the matching one of the destination, shifts the pair right by a per-element count and keeps the lower half. | AVX10.1 |
| VPSHRDW | Joins each word of the second source above the matching one of the first, shifts the pair right by an immediate and keeps the lower half. | AVX10.1 |
| VPSHUFB | Rearranges bytes within each 128-bit lane using an index byte per result, which zeroes the byte when its top bit is set. | AVX, AVX2, AVX10.1 |
| VPSHUFBITQMB | Selects, for each byte of the second source, one bit of the matching quadword of the first and writes the bits to a mask register. | AVX10.1 |
| VPSHUFD | Rearranges doublewords within each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSHUFHW | Rearranges the upper four words of each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSHUFLW | Rearranges the lower four words of each 128-bit lane as an immediate selects. | AVX, AVX2, AVX10.1 |
| VPSIGNB | Negates, zeroes or keeps each signed byte of the first source as the matching byte of the second is negative, zero or positive. | AVX, AVX2 |
| VPSIGND | Negates, zeroes or keeps each doubleword of the first source as the matching one of the second is negative, zero or positive. | AVX, AVX2 |
| VPSIGNW | Negates, zeroes or keeps each signed word of the first source as the matching word of the second is negative, zero or positive. | AVX, AVX2 |
| VPSLLD | Shifts doublewords left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLDQ | Shifts each 128-bit lane left by a number of bytes given by an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLQ | Shifts quadwords left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSLLVD | Shifts each doubleword left by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSLLVQ | Shifts each quadword left by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSLLVW | Shifts each word left by the count in the matching element of the second source. | AVX10.1 |
| VPSLLW | Shifts words left by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRAD | Shifts doublewords right arithmetically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRAQ | Shifts quadwords right arithmetically by one count from a register or an immediate. | AVX10.1 |
| VPSRAVD | Shifts each doubleword right arithmetically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRAVQ | Shifts each quadword right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAVW | Shifts each word right arithmetically by the count in the matching element of the second source. | AVX10.1 |
| VPSRAW | Shifts words right arithmetically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLD | Shifts doublewords right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLDQ | Shifts each 128-bit lane right by a number of bytes given by an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLQ | Shifts quadwords right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSRLVD | Shifts each doubleword right logically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRLVQ | Shifts each quadword right logically by the count in the matching element of the second source. | AVX2, AVX10.1 |
| VPSRLVW | Shifts each word right logically by the count in the matching element of the second source. | AVX10.1 |
| VPSRLW | Shifts words right logically by one count from a register or an immediate. | AVX, AVX2, AVX10.1 |
| VPSUBB | Subtracts packed bytes, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBD | Subtracts packed doublewords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBQ | Subtracts packed quadwords, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPSUBSB | Subtracts packed signed bytes with signed saturation. | AVX, AVX2, AVX10.1 |
| VPSUBSW | Subtracts packed signed words with signed saturation. | AVX, AVX2, AVX10.1 |
| VPSUBUSB | Subtracts packed unsigned bytes with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPSUBUSW | Subtracts packed unsigned words with unsigned saturation. | AVX, AVX2, AVX10.1 |
| VPSUBW | Subtracts packed words, wrapping around on overflow. | AVX, AVX2, AVX10.1 |
| VPTERNLOGD | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at doubleword granularity. | AVX10.1 |
| VPTERNLOGQ | Computes any bitwise function of three inputs, given as an 8-bit truth table in an immediate, masked at quadword granularity. | AVX10.1 |
| VPTEST | Sets ZF if the AND of two XMM or YMM operands is all zeros and CF if the AND of the inverted first with the second is. | AVX |
| VPTESTMB | Sets a mask bit for each pair of bytes whose AND is not zero. | AVX10.1 |
| VPTESTMD | Sets a mask bit for each pair of doublewords whose AND is not zero. | AVX10.1 |
| VPTESTMQ | Sets a mask bit for each pair of quadwords whose AND is not zero. | AVX10.1 |
| VPTESTMW | Sets a mask bit for each pair of words whose AND is not zero. | AVX10.1 |
| VPTESTNMB | Sets a mask bit for each pair of bytes whose AND is zero. | AVX10.1 |
| VPTESTNMD | Sets a mask bit for each pair of doublewords whose AND is zero. | AVX10.1 |
| VPTESTNMQ | Sets a mask bit for each pair of quadwords whose AND is zero. | AVX10.1 |
| VPTESTNMW | Sets a mask bit for each pair of words whose AND is zero. | AVX10.1 |
| VPUNPCKHBW | Interleaves the high bytes of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHDQ | Interleaves the high doublewords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHQDQ | Interleaves the high quadwords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKHWD | Interleaves the high words of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLBW | Interleaves the low bytes of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLDQ | Interleaves the low doublewords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLQDQ | Interleaves the low quadwords of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPUNPCKLWD | Interleaves the low words of each 128-bit lane of two sources. | AVX, AVX2, AVX10.1 |
| VPXOR | Computes the bitwise XOR of two XMM or YMM sources into a separate destination (YMM with AVX2). | AVX, AVX2 |
| VPXORD | Computes the bitwise XOR of two vectors, masked at doubleword granularity. | AVX10.1 |
| VPXORQ | Computes the bitwise XOR of two vectors, masked at quadword granularity. | AVX10.1 |
| VRANGEPD | Computes the minimum, maximum, or value of smaller or larger magnitude of packed doubles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGEPS | Computes the minimum, maximum, or value of smaller or larger magnitude of packed singles, as an immediate selects along with the sign of the result. | AVX10.1 |
| VRANGESD | Computes the minimum, maximum, or smaller or larger magnitude of the low doubles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRANGESS | Computes the minimum, maximum, or smaller or larger magnitude of the low singles, as an immediate selects; the rest come from the first source. | AVX10.1 |
| VRCP14PD | Approximates the reciprocal of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRCP14PS | Approximates the reciprocal of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRCP14SD | Approximates the reciprocal of the low double of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCP14SS | Approximates the reciprocal of the low single of the second source with a relative error below 2^-14; the other elements come from the first source. | AVX10.1 |
| VRCP28PD | Approximates the reciprocals of the packed doubles of a ZMM register, with a relative error below 2^-28. | AVX512ER |
| VRCP28PS | Approximates the reciprocals of the packed singles of a ZMM register to within 2^-28, then rounds them to single precision. | AVX512ER |
| VRCP28SD | Approximates the reciprocal of the low double to within 2^-28; the upper half comes from the first source. | AVX512ER |
| VRCP28SS | Approximates the reciprocal of the low single to within 2^-28 before rounding; the rest comes from the first source. | AVX512ER |
| VRCPBF16 | Approximates the reciprocal of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRCPPH | Approximates the reciprocal of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRCPPS | Approximates the reciprocals of packed singles in an XMM or YMM register, with a relative error of at most 1.5 times 2^-12. | AVX |
| VRCPSH | Approximates the reciprocal of the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VRCPSS | Approximates the reciprocal of the low single to within 1.5 times 2^-12; the other elements come from the first source. | AVX |
| VREDUCEBF16 | Subtracts from each packed bfloat16 value its value rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.2 |
| VREDUCEPD | Subtracts from packed doubles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPH | Subtracts from packed half-precision values their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCEPS | Subtracts from packed singles their values rounded to the number of fraction bits an immediate gives, leaving the reduced argument. | AVX10.1 |
| VREDUCESD | Subtracts from the low double of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VREDUCESH | Subtracts from the second source's low half-precision value that value rounded to an immediate's precision; the rest come from the first source. | AVX10.1 |
| VREDUCESS | Subtracts from the low single of the second source its value rounded to the fraction bits an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALEBF16 | Rounds each packed bfloat16 value to the number of fraction bits an immediate gives. | AVX10.2 |
| VRNDSCALEPD | Rounds packed doubles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPH | Rounds packed half-precision values to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALEPS | Rounds packed singles to the number of fraction bits and with the rounding mode that an immediate gives. | AVX10.1 |
| VRNDSCALESD | Rounds the low double of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESH | Rounds the second source's low half-precision value to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VRNDSCALESS | Rounds the low single of the second source to the fraction bits and rounding mode an immediate gives; the rest come from the first source. | AVX10.1 |
| VROUNDPD | Rounds packed doubles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR. | AVX |
| VROUNDPS | Rounds packed singles in an XMM or YMM register to integral values, with the rounding mode of an immediate or MXCSR. | AVX |
| VROUNDSD | Rounds the low double of the second source to an integral value, by an immediate or MXCSR; the upper half comes from the first. | AVX |
| VROUNDSS | Rounds the low single of the second source to an integral value, by an immediate or MXCSR; the rest comes from the first. | AVX |
| VRSQRT14PD | Approximates the reciprocal square root of packed doubles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14PS | Approximates the reciprocal square root of packed singles with a relative error below 2^-14. | AVX10.1 |
| VRSQRT14SD | Approximates the reciprocal square root of the second source's low double, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRT14SS | Approximates the reciprocal square root of the second source's low single, relative error below 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRT28PD | Approximates the reciprocal square roots of the packed doubles of a ZMM register, with a relative error below 2^-28. | AVX512ER |
| VRSQRT28PS | Approximates the reciprocal square roots of packed singles to within 2^-28, then rounds them to single precision. | AVX512ER |
| VRSQRT28SD | Approximates the reciprocal square root of the low double to within 2^-28; the upper half comes from the first source. | AVX512ER |
| VRSQRT28SS | Approximates the reciprocal square root of the low single to within 2^-28 before rounding; the rest comes from the first source. | AVX512ER |
| VRSQRTBF16 | Approximates the reciprocal square root of each packed bfloat16 value with a relative error below 2^-8 + 2^-14. | AVX10.2 |
| VRSQRTPH | Approximates the reciprocal square root of packed half-precision values with a relative error below 2^-11 + 2^-14. | AVX10.1 |
| VRSQRTPS | Approximates the reciprocal square roots of packed singles in an XMM or YMM register, to within 1.5 times 2^-12. | AVX |
| VRSQRTSH | Approximates 1/sqrt(x) for the second source's low half-precision value, relative error below 2^-11 + 2^-14; the rest come from the first source. | AVX10.1 |
| VRSQRTSS | Approximates the reciprocal square root of the low single to within 1.5 times 2^-12; the other elements come from the first source. | AVX |
| VSCALEFBF16 | Multiplies each packed bfloat16 value by 2 raised to the floor of the corresponding value of the second source. | AVX10.2 |
| VSCALEFPD | Multiplies packed doubles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPH | Multiplies packed half-precision values by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFPS | Multiplies packed singles by 2 raised to the floor of the matching values of the second source. | AVX10.1 |
| VSCALEFSD | Multiplies the low double by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCALEFSH | Multiplies the low half-precision value by 2 to the floor of the second source's low value; the other elements come from the first source. | AVX10.1 |
| VSCALEFSS | Multiplies the low single by 2 raised to the floor of the low value of the second source; the other elements come from the first source. | AVX10.1 |
| VSCATTERDPD | Stores doubles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERDPS | Stores singles to memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERPF0DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VSCATTERPF0DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VSCATTERPF0QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VSCATTERPF0QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the first-level cache, under a mask. | AVX512PF |
| VSCATTERPF1DPD | Prefetches, with intent to write, the doubles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VSCATTERPF1DPS | Prefetches, with intent to write, the singles that a vector of doubleword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VSCATTERPF1QPD | Prefetches, with intent to write, the doubles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VSCATTERPF1QPS | Prefetches, with intent to write, the singles that a vector of quadword indices addresses into the second-level cache, under a mask. | AVX512PF |
| VSCATTERQPD | Stores doubles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSCATTERQPS | Stores singles to memory at addresses formed with a vector of 64-bit indices, for the elements a mask selects. | AVX10.1 |
| VSHA512MSG1 | Performs the first half of the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512MSG2 | Completes the SHA-512 message schedule computation for the next four message quadwords. | SHA512 |
| VSHA512RNDS2 | Performs two rounds of SHA-512 (and SHA-384) on the working state, using precomputed message and round-constant sums. | SHA512 |
| VSHUFF32X4 | Picks 128-bit blocks of singles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFF64X2 | Picks 128-bit blocks of doubles from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI32X4 | Picks 128-bit blocks of doublewords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFI64X2 | Picks 128-bit blocks of quadwords from the two sources as an immediate selects, the lower half of the result from the first source. | AVX10.1 |
| VSHUFPD | Picks doubles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX, AVX10.1 |
| VSHUFPS | Picks singles from the two sources for each position within each 128-bit lane, as an immediate selects. | AVX, AVX10.1 |
| VSM3MSG1 | Performs the first part of the SM3 message expansion for the next four message words. | SM3 |
| VSM3MSG2 | Completes the SM3 message expansion for the next four message words. | SM3 |
| VSM3RNDS2 | Performs two rounds of the SM3 hash function, starting at the round number in an immediate. | SM3 |
| VSM4KEY4 | Performs four rounds of SM4 key expansion in each 128-bit lane. | SM4 |
| VSM4RNDS4 | Performs four rounds of SM4 encryption in each 128-bit lane. | SM4 |
| VSQRTBF16 | Computes the square root of each packed bfloat16 value, rounding to nearest, with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSQRTPD | Computes the square root of packed doubles. | AVX, AVX10.1 |
| VSQRTPH | Computes the square root of packed half-precision values. | AVX10.1 |
| VSQRTPS | Computes the square root of packed singles. | AVX, AVX10.1 |
| VSQRTSD | Computes the square root of the low double of the second source; the other elements come from the first source. | AVX, AVX10.1 |
| VSQRTSH | Computes the square root of the low half-precision value of the second source; the other elements come from the first source. | AVX10.1 |
| VSQRTSS | Computes the square root of the low single of the second source; the other elements come from the first source. | AVX, AVX10.1 |
| VSTMXCSR | Stores the MXCSR register, the SSE control and status bits, to memory; the VEX form of STMXCSR. | AVX |
| VSUBBF16 | Subtracts packed bfloat16 values, rounding to nearest even with denormals treated as zero and without floating-point exceptions. | AVX10.2 |
| VSUBPD | Subtracts packed doubles. | AVX, AVX10.1 |
| VSUBPH | Subtracts packed half-precision values. | AVX10.1 |
| VSUBPS | Subtracts packed singles. | AVX, AVX10.1 |
| VSUBSD | Subtracts the low doubles; the other elements come from the first source. | AVX, AVX10.1 |
| VSUBSH | Subtracts the low half-precision values; the other elements come from the first source. | AVX10.1 |
| VSUBSS | Subtracts the low singles; the other elements come from the first source. | AVX, AVX10.1 |
| VTESTPD | Sets ZF and CF like VPTEST, but from the sign bits of the packed doubles alone. | AVX |
| VTESTPS | Sets ZF and CF like VPTEST, but from the sign bits of the packed singles alone. | AVX |
| VUCOMISD | Compares the low doubles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX, AVX10.1 |
| VUCOMISH | Compares the low half-precision values and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX10.1 |
| VUCOMISS | Compares the low singles and sets ZF, PF and CF, clearing OF, SF and AF; only a signaling NaN raises an invalid exception. | AVX, AVX10.1 |
| VUCOMXSD | Compares the low double-precision values of two operands like VCOMXSD but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSH | Compares the low half-precision values of two operands like VCOMXSH but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUCOMXSS | Compares the low single-precision values of two operands like VCOMXSS but signals an invalid exception only for signaling NaNs. | AVX10.2 |
| VUNPACKB | Unpacks tightly packed 2- to 7-bit fields into bytes, zero- or sign-extended, with the field size and start given by an immediate. | AVX10_V2_AUX |
| VUNPCKHPD | Interleaves the high doubles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKHPS | Interleaves the high singles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKLPD | Interleaves the low doubles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VUNPCKLPS | Interleaves the low singles of each 128-bit lane of two sources. | AVX, AVX10.1 |
| VXORPD | Computes the bitwise XOR of packed doubles. | AVX, AVX10.1 |
| VXORPS | Computes the bitwise XOR of packed singles. | AVX, AVX10.1 |
| VZEROALL | Zeroes vector registers 0 to 15 (0 to 7 outside 64-bit mode) in full. | AVX |
| VZEROUPPER | Zeroes the bits above 127 of vector registers 0 to 15, which compilers do before running or calling code that may use legacy SSE. | AVX |
| WBINVD | Writes every modified line of the caches back to memory and invalidates the caches; ring 0 only. | System |
| WBNOINVD | Writes every modified line of the caches back to memory but keeps the lines cached; ring 0 only. | WBNOINVD |
| WRFSBASE | Writes the FS base from a register, so a thread can change its TLS pointer without a system call; 64-bit mode, with CR4.FSGSBASE. | FSGSBASE |
| WRGSBASE | Writes the GS base from a register; 64-bit mode, when the kernel set CR4.FSGSBASE. | FSGSBASE |
| WRMSR | Writes EDX:EAX to the model-specific register that ECX selects; ring 0 only and, unlike WRMSRNS, serializing. | System |
| WRMSRLIST | Writes up to 64 model-specific registers from a table in memory to the addresses listed in a second table, selected by a bit mask in RCX. | MSRLIST |
| WRMSRNS | Writes a model-specific register like WRMSR but without serializing the processor; the MSR_IMM form takes the MSR number as an immediate. | WRMSRNS, MSR_IMM, APX |
| WRPKRU | Writes PKRU from EAX, changing which of the 16 protection keys allow access and writes, without a system call; ECX and EDX must be zero. | PKU |
| WRSSD | Writes a 32-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | CET, APX |
| WRSSQ | Writes a 64-bit value to the current privilege level's shadow stack, where the operating system allows such writes. | CET, APX |
| WRUSSD | Lets ring-0 code write a 32-bit value to a user-mode shadow stack. | CET, APX |
| WRUSSQ | Lets ring-0 code write a 64-bit value to a user-mode shadow stack. | CET, APX |
| XABORT | Aborts an RTM transaction, discarding its effects and resuming at the XBEGIN fallback with an 8-bit reason code in EAX. | RTM |
| XADD | Exchanges a register with the destination and stores their sum in the destination; with LOCK it is the atomic fetch-and-add. | General-purpose |
| XBEGIN | Starts an RTM transaction; if it aborts, its effects are rolled back and execution goes to the fallback address, with the reason in EAX. | RTM |
| XCHG | Swaps two operands; with a memory operand it is atomic even without a LOCK prefix. | General-purpose |
| XCRYPTCBC | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CBC mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XCRYPTCFB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in CFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XCRYPTCTR | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in counter mode; rAX, rBX and rDX point to counter, key and control word; VIA PadLock. | VIA PadLock |
| XCRYPTECB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in ECB mode, the key at [rBX] and a control word at [rDX]; VIA PadLock. | VIA PadLock |
| XCRYPTOFB | Encrypts or decrypts rCX blocks from [rSI] to [rDI] with AES in OFB mode; rAX, rBX and rDX point to IV, key and control word; VIA PadLock. | VIA PadLock |
| XEND | Commits an RTM transaction, making all of its memory updates visible at once. | RTM |
| XGETBV | Reads the extended control register that ECX selects into EDX:EAX; XCR0 says which state components the OS lets XSAVE manage. | XSAVE |
| XLAT | Replaces AL with the byte at RBX plus AL, a table lookup; XLATB is the spelling without operands. | General-purpose |
| XOR | Computes the bitwise exclusive OR of two operands; APX adds three-operand forms and forms that leave the flags unchanged. | General-purpose, APX |
| XORPD | Computes the bitwise XOR of two XMM operands, as packed doubles; with the same register twice it zeroes it. | SSE2 |
| XORPS | Computes the bitwise XOR of two XMM operands, as packed singles; with the same register twice it zeroes it. | SSE |
| XRESLDTRK | Ends a TSXLDTRK region of an RTM transaction, so that later loads join the transaction's read set again. | TSXLDTRK |
| XRSTOR | Restores the state components that XCR0 and EDX:EAX select from an XSAVE area, setting those the area marks unused to their initial state. | XSAVE |
| XRSTORS | Restores user and supervisor state components from a compacted XSAVE area written by XSAVES; ring 0 only. | XSAVES |
| XSAVE | Saves the state components that XCR0 and EDX:EAX select, such as the x87, SSE and AVX registers, to a 64-byte aligned XSAVE area. | XSAVE |
| XSAVEC | Saves selected state components in the compacted format of the XSAVE area, leaving out those in their initial state. | XSAVEC |
| XSAVEOPT | Saves selected state components like XSAVE but may skip those unchanged since the last XRSTOR or in their initial state. | XSAVEOPT |
| XSAVES | Saves selected user and supervisor state components in the compacted format, skipping unchanged and initial ones; ring 0 only. | XSAVES |
| XSETBV | Writes EDX:EAX to the extended control register that ECX selects, such as XCR0, which enables AVX and other XSAVE state; ring 0 only. | XSAVE |
| XSHA1 | Hashes the data at [rSI] with SHA-1 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock. | VIA PadLock |
| XSHA256 | Hashes the data at [rSI] with SHA-256 into the state at [rDI]; rCX gives the total length and rAX the bytes already hashed; VIA PadLock. | VIA PadLock |
| XSTORE | Stores random bytes from the processor's random number generator at [rDI], at the rate EDX selects, and returns their count in EAX; VIA PadLock. | VIA PadLock |
| XSUSLDTRK | Starts a region of an RTM transaction whose loads stay out of its read set, so they cannot cause conflicts. | TSXLDTRK |
| XTEST | Clears ZF inside an RTM or HLE transaction and sets it outside one. | RTM |
Reading the tables
The tables follow the notation of Intel’s manuals, with a few additions for information that XED records.
Instruction
Operands are in Intel order, destination first.
r8,r16,r32,r64- General-purpose registers of that width.
r16/32/64means the operand size is chosen by the prefixes: 66 for 16 bits, REX.W (or EVEX.W) for 64 bits, 32 bits otherwise. m8tom512,m16/32/64- A memory operand of that many bits.
imm8,imm16/32,imm64- An immediate value encoded in the instruction.
rel8,rel32,rel16/32- A branch target as a signed offset from the next instruction.
m16:16/32/64,ptr16:16/32- A far pointer, a 16-bit segment selector and an offset of 16, 32 or 64 bits, in memory or as an immediate.
AL,eAX,rAX,DX- A fixed register.
eAXis AX or EAX andrAXAX, EAX or RAX, by operand size. sreg,cr,dr- A segment, control or debug register.
m- A memory operand of which only the address matters, as for LEA.
mem,m512byte- A memory area named by what it holds: the XSAVE area, whose size depends on the state it saves, or the 512 bytes of FXSAVE.
m16&32,m16&64,m16&16,m32&32- Two values in memory: a 16-bit limit and a base, as LGDT loads, or the two bounds of BOUND.
bnd,mib- An MPX bound register, and a memory operand whose base and index registers MPX uses separately.
st(i),ST(0),mm- An x87 register, counted from the top of the register stack, the top itself, and a 64-bit MMX register.
m32fp,m16int,m80bcd,m28byte- x87 memory operands, by size and type: a floating-point value, a signed integer, an 18-digit packed BCD integer, or the x87 environment or state, whose size depends on the operand size.
xmm,ymm,zmm,k,tmm- A 128-, 256- or 512-bit vector register, an AVX-512 mask register, or an AMX tile register.
{k},{k}{z}- The destination is written under a mask register; with
{z}, masked-off elements can be zeroed instead of kept. m512/m32bcst- Either a full vector in memory or one element that is broadcast to every position (EVEX.b set).
{er},{sae}- The register form accepts a rounding mode in the instruction (embedded rounding), or suppresses floating-point exceptions.
vm32x,vm64z- A vector of addresses for gathers and scatters: 32- or 64-bit indices in an xmm, ymm or zmm register (VSIB addressing).
sibmem- A memory operand that must be encoded with a SIB byte; AMX tile loads and stores use its index register as the row stride.
{dfv}- The flags that APX’s CCMP and CTEST set when their condition is false, encoded in the instruction.
cc,scc- A condition code. Mnemonics that differ only in their condition, such
as CMOVZ and CMOVNZ, share a page; the condition is part of the
opcode (
40+cc) or of the EVEX prefix (SC=scc). LOCK,REP- The form carries the prefix. XED lists these as separate instructions; here they appear on the page of the base mnemonic, as do the spellings of one instruction for each operand size, such as MOVSB to MOVSQ on the page of MOVS.
Encoding
66,F2,F3,NP- A prefix that is part of the opcode; NP means none of them is allowed.
67- The address-size prefix, for a form that uses a smaller address size than the mode’s default, such as JECXZ, which tests ECX, in 64-bit mode.
REX.W,REX2- A REX prefix with W set, or APX’s two-byte REX2 prefix (D5).
0F,0F 38,0F 3A- The escape bytes of the legacy opcode maps.
VEX.256.66.0F38.W0- A VEX or EVEX prefix with its fields: vector length (128, 256, 512;
LZorLLZmust be zero andL1one, for instructions without vector operands;LIGis ignored), implied prefix, opcode map (0F, 0F38, 0F3A, or MAP4 to MAP7) and the W bit (W0,W1,WIGfor ignored). SCALABLE- In APX forms of legacy instructions, EVEX.W selects 64-bit operands and the implied 66 prefix selects 16-bit ones, as REX.W and 66 do.
/r,/0to/7,C0- A ModR/M byte with a register operand in its reg field, with a fixed value in the reg field that extends the opcode, or a fixed ModR/M byte.
+r,+cc- A register number or a condition code added to the opcode byte.
C0+i- An x87 register: the number i of ST(i) added to the second byte
(
D8 C0+iis FADD ST(0), ST(i)). ib,iw,id,io,/is4- An immediate of 1, 2, 4 or 8 bytes;
iw/iddepends on the operand size./is4is an immediate byte whose upper four bits name a register. ND=1,NF=1,NF=0/1- APX bits of the EVEX prefix: ND selects the new data destination, NF
suppresses the flag updates.
NF=0/1means the form exists both ways. (without BMI1)- The bytes mean this instruction only on processors without the named feature; on those with it, they are another instruction. F3 0F BC is BSF without BMI1 and TZCNT with it.
Tags
- NDD
- APX new data destination: the result goes to a separate register and the other operands are only read.
- NF
- APX “no flags”: the instruction leaves the arithmetic flags unchanged.
- ZU
- APX “zero upper”: the destination register is written in full, with zeros above the result.
- 64-bit mode only, not in 64-bit mode
- Where the form can be used. APX forms are always 64-bit only.
- undocumented
- An encoding that Intel’s manual does not list but that XED decodes as this instruction, such as the x87 alias DF D0+i for FSTP ST(i).
Requires
Each form belongs to an ISA set of XED. The column names the CPUID features that enable it; when there are alternatives, any one of them is enough. AVX-512 forms, for example, need either their AVX-512 feature bits or AVX10.1. Each page lists the exact CPUID bits and the processors that XED’s chip model gives each ISA set, followed by AMD’s processors after Zen 2 from the CPU data of this site.
Latency and throughput
The table after the forms gives what the scheduling models of LLVM
23.1.2 (commit 85ac56026243)
say about each form, as llvm-mca
reports them: its latency, the cycles from its inputs to its result,
and its reciprocal throughput, the cycles per instruction when many
independent ones follow each other. Under them are the ports or units
that the model charges the form to, such as p01 for ports 0 and 1 of
an Intel core or FP2 FP3 for two of the floating-point pipes of an AMD
one. These are the models that LLVM’s compilers schedule code with,
not measurements, and they can be wrong. The latency of a memory form
counts from its address, so it includes the load, and its ports leave
out the units of the load or store itself. A cell shows no ports where
the model names none, and some models give register moves a latency or
a reciprocal throughput of 0.
A column is a form at one operand size. Forms that give the same
numbers on every model share a column, and so do the masked, zeroing,
broadcast and rounding variants of an EVEX form, except those that time
otherwise, which get a column of their own, labelled “with a mask” or
the like. A row is a model, or the models that give the same numbers
for every column, named after the processor each was written for.
llvm-mca times any instruction on any model, so a model has a cell
only for the forms that one of its own processors has, as the
processor lists of the pages give them; a dash marks the others. Where
a page would grow past its size budget, its table leaves out the ports
of the forms that only load or store, or all of its ports, and its
caption says so.
LLVM has no model of its own for Zen 5 or Zen 6 and schedules them with its Zen 4 model, so the Zen 4 row stands for them too. AMD’s latency spreadsheet for Zen 5, part of its optimization guide 58455, differs from that row where the newer core is wider: simple integer instructions such as ADD run 6 per cycle on its six ALUs where the model allows 4 (row 1970), two-operand IMUL 3 per cycle on its three multipliers where the model allows 1 (row 2021), ZMM forms such as VADDPS 2 per cycle on its 512-bit datapath where the model, which splits them in halves as Zen 4 does, allows 1 (row 3), a floating-point add such as ADDPS takes 2 cycles where the model gives 3 (row 1450), and simple shuffles such as PSHUFD run on four pipes where the model has two (row 1581). Where a cell disagrees with that spreadsheet and with AMD’s Zen 4 one (57647) alike, the model is likely wrong for Zen 4 as well: the cell then has a numbered mark, and a note under the table gives the rows of both spreadsheets. So does a cell where a model contradicts its own source. Not every page has been checked yet.
Two choices of the models are not marked on the pages. The Alder Lake, Sapphire Rapids and Lunar Lake models give every store a latency of 12 cycles (X86SchedAlderlakeP.td, line 420), where the other models give 1. The Piledriver model gives an aligned 256-bit store a reciprocal throughput of 18, close to the one such store per 17 cycles that Agner Fog measured (his microarchitecture guide, section 21.9), but gives its unaligned 256-bit stores 1.
No row of any table comes from:
GenericPostRAModel(NetBurst (Prescott, Nocona)): it gives no latencies or units of its own.C864GM4Model,C864GM7ModelandC864GM8Model: Hygon's C86-4G processors have no page under /cpus/.- K8 (Hammer): X86.td defines k8 with a Proc line, which has no scheduling model.
- K10 (Family 10h): X86.td defines amdfam10 with a Proc line, which has no scheduling model.
- Bobcat: X86.td defines btver1 with a Proc line, which has no scheduling model.
- LuJiaZui, Century Avenue (Shijidadao): X86.td has no -mcpu for Zhaoxin's processors.
Data flow
The pages of vector instructions draw where the elements of the
sources go. Each row is an operand, named as Intel’s manuals number
them (xmm1 is the first operand, usually the destination), with
element 0 on the right; the result’s name is in blue, and each source
has a letter and a colour of its own. Forms that move their elements
the same way share one drawing, made for one vector length and noted
for the others, and a pattern that repeats in each 128-bit lane is
drawn for one lane. Where the result depends on a control value, such
as an immediate, an index vector or a mask, the drawing works through
an example. Every example was run on an AMD EPYC 9645 (Zen 5)
processor, as the instruction itself or, where that processor lacks
it, as another that moves elements the same way, and the drawing shows
what came out. The examples of XOP’s permutes, which no processor here
has, were not run: the page’s pseudocode works them out, and the
drawing says so. The words under each drawing say the same, and end
with the drawn result element by element, highest first.
A drawing has at most 16 columns, and on a phone at most 8: there, a row of more elements takes two lines, its high elements above and the lower line set half a column to the right, so that each wire passes the other line between two cells. So is a drawing drawn on every screen where 16 columns would leave its cells too narrow for their labels. A zeroed rest of the register that two lines have no room for, as in a conversion to 4-bit elements, is one cell at the left of the upper line.
a3,b0- Element 3 of source a, or element 0 of source b: where an element of the result comes from. A wire joins the two.
r0,sum,+=- An element computed from those its wires come from:
sumadds a group of them, and+=adds them to the destination’s old value. 0, grey- An element that is zeroed.
- hatched
- An element left as it was: masked off under merging, or memory that is not written.
- filled and open dots
- The bits of a mask register,
k1: 1 is filled and 0 open. The wire of each element goes through its bit. …- The row goes on to the left; only its low elements are drawn.
- bars
- Windows: the bytes or bits of a source that one element of the result is computed from, such as the four bytes that each word of a sum of absolute differences takes. Each bar’s wire starts at the dot on it; overlapping bars sit one above the other.
- ticks
- The bytes of a source drawn in doublewords, or its bits where it is drawn in bytes.
- grey upper part
- The extension of a widened element: zeros, or copies of the sign bit.
Operation
The pages of the instructions done so far say what each form does, in pseudocode of our own: a small part of Python that the tests run. Each block covers a group of forms, named above it, and describes 64-bit mode unless the forms exist only outside it. The line under a block gives the processors that ran it: their results, for edge cases and random inputs, were recorded with a probe, such as on an AMD EPYC 9645 (Zen 5), and the tests run the block on the same inputs and require the same results; where the two disagree, the processor decides. A block that cannot run in user mode, such as a move to a control register, is written the same way and says it was not run. So are the APX forms, which none of these processors has. Where every case of a block raised an exception, as a privileged instruction does at CPL 3, where the probe runs, or IN without the right to its port, the line says so: the cases checked the tests that come first, not what the instruction does once they pass. So does the line of an instruction that the probe ran where CPUID reported no support for its extension, to see what the processor made of its bytes: mostly #UD, or nothing where the bytes are a hint, as ENDBR64’s are. Those cases checked its feature test. The probe runs under a hypervisor, which may hide from CPUID a feature that the processor has.
dest,src,count- The operands of the syntax, in its order.
dest.read()anddest.write(v)read and write one; an operand used as a value, as indest + src, is read..bitsis its width,.is_memorywhether it is in memory, and.numberthe number of a register, as in CR4. LEA’ssrc.addressis the address it computes, base plus index times scale plus displacement, at the address size; memory is not read. rax,eax,ax,al,ah- Registers by name. Writing a 32-bit register clears bits 63:32 of its 64-bit register; writing an 8- or 16-bit one keeps the other bits. The new destination of an APX NDD form, and the destination of a ZU form or of CFCMOVcc, are written whole, bits 63:OSIZE cleared, at every operand size.
rAX- The accumulator of the operand size: AL, AX, EAX or RAX, as the syntax writes it.
aCX,aSI,aDI- RCX, RSI and RDI at the address size: the count and pointers of the string instructions and of LOOP, which a 67 prefix makes ECX, ESI and EDI.
rip- The address of the next instruction: the instruction’s own address
plus its length, which CALL pushes. Assigning
ripjumps there. cf,pf,af,zf,sf,of- The status flags, 0 or 1.
flags = add_flags(a, b)sets all six as an addition would, andsub_flagsas a subtraction would. df,tf,if_,iopl,ac,id,rflags- The other flags of RFLAGS by name,
if_for IF (ifis a word of Python) and IOPL as a number from 0 to 3;rflagsis the whole register as a number, as PUSHF pushes it. UNDEFINED- What a flag, a register or memory holds when the instruction leaves it undefined. A processor leaves some value there, which must not be relied on, and the tests do not compare it.
OSIZE,nf,CPL,dfv- The operand size in bits (8, 16, 32 or 64), the NF bit of an APX
form, the current privilege level, and the
{dfv}of CCMPscc and CTESTscc: the flags they set when their condition is false, OF, SF, ZF and CF as bits 3 to 0. if INTEL:,if AMD:- Where Intel’s and AMD’s processors do different things, a block
splits on the vendor, and only in an
ifof its own, whoseelseis the other vendor: a 66 prefix on a near branch in 64-bit mode, which Intel’s processors ignore and AMD’s take for a 16-bit operand size, is one such place. Each branch’s comment gives its source: Intel’s SDM or AMD’s APM, by section and revision, or a result recorded on a processor. The tests run each recorded case as its processor’s vendor, and each branch on cases worked out by hand for both vendors; the line under a block names the vendors whose branches no processor of theirs has run. cond(CC)- 1 when the flags meet the condition of a conditional instruction.
The pages of CMOVcc, SETcc, Jcc and their kin have one block for all
the conditions, and
CCis the one in the mnemonic, in lower case:nbefor CMOVNBE, which is also spelled CMOVA.o,b,z,sandphold when OF, CF, ZF, SF or PF is 1;bewhen CF or ZF is;lwhen SF and OF differ;lewhen ZF is 1 or SF and OF differ. With annin front (nbe), a condition holds when the one without does not.tandf, of CCMPscc and CTESTscc, always and never hold.cond(CC, f)tests flags that the block computes, as inf = sub_flags(a, b), instead of those from before the instruction. sext(x),signed(x),low(x),msb(x),parity(x)xsign-extended from its width to the operand size (an immediate as encoded, such as an imm8);xas a signed number of its width, so that an imm8 of 0xFF is -1; its low OSIZE bits, its top bit, and 1 when its low byte has an even number of 1 bits, as PF.fault(GP, 0)- The instruction raises an exception, here #GP(0), and writes none of its registers. The exceptions go by their names without the #: DE, DB, BP, OF, BR, UD, NM, TS, NP, SS, GP, PF, MF, AC, XM and CP.
load_segment(dest, sel),load_segment(fs, sel)- Loads a segment register with a selector and the descriptor it names
in the GDT or LDT, checking that the descriptor lies within the table,
has a type, privilege levels (RPL, DPL and CPL) and present bit that
allow the load, and raising #GP, #SS or #NP otherwise. A null selector
loads DS, ES, FS or GS as unusable, but not SS at CPL 3. Volume 3 of
Intel’s SDM has the full rules. The register is an operand, or named
as
fsis for LFS, whose syntax leaves it out. gate(n),descriptor(sel)- Entry n of the interrupt descriptor table (IDT), 16 bytes, and the 8-byte segment descriptor that a selector names in the GDT, or in the LDT when its TI bit is set, as numbers whose fields the block takes apart: a gate’s type in bits 43:40 (1110b an interrupt gate, 1111b a trap gate), DPL in 46:45 and P, present, in 47; a segment’s type in 43:40 (bit 43 set for code, then bit 42 conforming and 41 readable; for data, expand-down and writable), S in 44, DPL in 46:45, P in 47 and L, 64-bit code, in 53. An entry past its table’s limit raises #GP, with 8n + 2 as the error code for a gate, the selector for a descriptor.
in_table(sel),gdtr,idtr,ldtr,tr- 1 when the descriptor a selector names lies within its table, so
that
descriptor(sel)reads it without a fault, as LAR and LSL ask before they read one; the registers of the GDT and the IDT, their base address in bits 79:16 and limit in bits 15:0, as SGDT stores them; the selectors in LDTR and TR, of the LDT and the task state segment. LGDT, LIDT, LLDT and LTR assign them. set_descriptor(sel, d)- Writes
d, 8 bytes, to the entry of the GDT or LDT that a selector names, as LTR marks the descriptor of the task state segment busy. interrupt(n)- Calls the handler of vector n through its gate, as an exception is delivered, but with no error code. In 64-bit mode the handler’s code segment is checked; a more privileged handler gets the stack that the TSS gives for its privilege level, or the TSS’s IST entry that the gate names; SS, RSP, RFLAGS, CS and the address of the next instruction are pushed; TF, NT and RF are cleared, and IF too through an interrupt gate. The tests stop there, with the exception of the vector, such as #BP, as the probe records it. Its cases run as a Linux process, whose tables the tests use: only the gates of vectors 3, 4 and 0x80 have DPL 3, and 0x33, 0x23 and 0x2b are the 64-bit and 32-bit code segments and the data segment of user programs.
load(a, 64),store(a, 64, v),dest.address- Memory at an address, here 64 bits of it: the stack, the strings,
the bits past the operand of BT.
dest.addressis where a memory operand is. A store is seen by the loads after it, which matters when the source and destination of a string move overlap. canonical(a),writable(a),readable(a)- Whether an address is canonical: bits 63:47 all equal, or bits 63:56 with 5-level paging, which CR4.LA57 turns on; and whether a write, or a read, at address a would succeed.
io_allowed(p, 8),io_read(p, 8),io_write(p, 8, v)- The I/O ports of IN, OUT, INS and OUTS, 0 to FFFFH, which are not
memory; here 8 bits at port
p, or 16 or 32 bits at the ports frompup.io_allowedsays whether the I/O permission bit map of the task state segment clears the bits of those ports, which the instructions ask only when CPL is greater than IOPL;io_readgives what the port gives, andio_writewrites to it. A device may give another value to every read, and a read or a write may do more. r = cpuid_leaf(leaf, sub),r[0],cpuid_faulting- The processor’s answer to CPUID for a leaf and sub-leaf:
r[0]tor[3]are the 32-bit values it returns in EAX, EBX, ECX and EDX, and a leaf without sub-leaves ignoressub. The answers are the processor’s own, and under a hypervisor the hypervisor’s, so the tests check only what every processor does: four 32-bit values, nothing else changed.cpuid_faultingis 1 when the operating system has CPUID raise #GP outside CPL 0. tsc(),tsc_aux,pru(n)- The time-stamp counter, 64 bits, which counts from the processor’s
reset at a rate of its own (under a hypervisor, as the hypervisor
offsets and scales it); the 32 bits of the TSC_AUX register, which
the operating system sets for each CPU (Linux to the CPU’s number,
plus its node’s times 4096); and the register that RDPRU reads for
n, MPERF for 0 and APERF for 1. These values are the processor’s or time’s: the tests take them back from what a recorded case wrote and check the rest, such as bits 63:32 of RAX and RDX cleared. random_ready(),random(n),seed_ready(),seed(n)- Whether the random number generator behind RDRAND has a number ready
for the instruction, 1 or 0, and
nbits of that number; the same for the generator behind RDSEED. The numbers are random: the tests take them, and whether one was ready, back from a recorded case’s destination and CF, and check the rest. os_timeout(t)- 1 when a wait of UMWAIT or TPAUSE, which lasts until the time-stamp
counter reaches
tunless an event ends it sooner, ends because the operating system’s limit runs out first, else 0: time’s to decide, liketsc(). mxcsr,mxcsr_mask- MXCSR, the control and status register of the SSE and AVX floating-point instructions, and the bits of it that the processor supports, as FXSAVE stores them: FFFFH on Intel’s processors, 2FFFFH on Zen 5, whose bit 17 is AMD’s mask of the misaligned-operand exception.
xmm[i],ymm[i],zmm[i],opmask[i]- Vector register
ias 128, 256 or 512 bits, and mask registeri(k0 to k7), by number, as the instructions that save and load them all reach them.xmm[i] = vwrites bits 127:0 and keeps the others, as a legacy SSE instruction does;zmm[i] = vwrites all 512.ymm[i].dq[1]is bits 255:128, as the element views below read them. xcr0,xss,xinuse- XCR0 and the IA32_XSS register, which say which state components the operating system lets the XSAVE family manage (x87, SSE, AVX, the three of AVX-512, PKRU …; the supervisor ones in IA32_XSS), and XINUSE, those not in their initial configuration, as XGETBV reads it with ECX = 1, SSE among them whenever MXCSR is not 1F80H.
xsave_offset(i, xcomp)- Where state component
i(from 2 up) is in an XSAVE area whose header has XCOMP_BV =xcomp: with bit 63 clear (the standard format), at the offset that CPUID leaf 0DH gives it; with it set (the compacted format), after the components ofxcompbelow it, from byte 576, each as large as CPUID says, and on a 64-byte boundary where CPUID asks for one. fsbase,gsbase,pkru- The base addresses of FS and GS, which an FS or GS prefix adds to an address, and PKRU, the access rights of user pages by protection key: for key k, bit 2k set denies every access and bit 2k + 1 writes.
msr[n],msr_exists(n),msr_allows(n, v)- Model-specific register
n, 64 bits, by its number, as RDMSR and WRMSR take it in ECX:msr[n] = vwrites it. Each processor has a set of its own:msr_existssays whether it has registern, andmsr_allowswhether that register may take the valuev, which may set no bit the processor reserves there and must be canonical where the register holds an address. The FS and GS bases are registers C000_0100H and C000_0101H. The probe’s cases run as a Linux process, whose EFER is D01H (long mode, SYSCALL and no-execute pages enabled) and has SVME set as well on the Zen 5, a guest of KVM, which keeps it set: values that the tests infer from the faults the probe recorded, since user mode cannot read them. efer,star,lstar,cstar,fmask,kernel_gs_base,sysenter_cs- Model-specific registers by name: EFER (C000_0080H), whose bit 0,
SCE, enables SYSCALL; STAR, LSTAR, CSTAR and SFMASK (C000_0081H to
C000_0084H), the selectors, the entry points of 64-bit and
compatibility mode and the flags that SYSCALL clears;
KernelGSbase (C000_0102H), which SWAPGS exchanges with the GS base;
and SYSENTER_CS, with
sysenter_espandsysenter_eip(174H to 176H), the selector, stack and entry point of SYSENTER. pmc(n),pmc_exists(n)- The performance-monitoring counter that RDPMC reads for
n, and whether the processor has it. What a counter holds is the processor’s, as the time-stamp counter’s is: the tests take it back from what a recorded case wrote. enqueue(a, v),mcommit_ok()- ENQCMD’s store of a 64-byte command
vto the device register at addressa: 1 when the device takes it, and 0 when it asks to try again or whenais no such register, ordinary memory included, which the store leaves as it was; and whether every store before MCOMMIT reached its memory without an error, the platform’s answer. smm,smm_restore()- 1 in system-management mode, which an SMI enters; and RSM’s way out of it: the registers, RIP and RFLAGS that the SMI saved in SMRAM are loaded back, and the mode ends.
ssp,u_cet,s_cet,pl0_ssp- CET’s shadow stack pointer; the model-specific registers IA32_U_CET
(6A0H) and IA32_S_CET (6A2H), which turn CET’s parts on at CPL 3 and
below it: bit 0 shadow stacks, 1 WRSS, 2 indirect branch tracking,
10 SUPPRESS and 11 TRACKER, which an indirect CALL or JMP sets and
ENDBR64 clears; and IA32_PL0_SSP (6A4H), the shadow stack pointer of
CPL 0. CR4.CET, bit 23 of
cr4, turns CET on as a whole. ss_load(a, 64),ss_store(a, 64, v),ss_store_user(a, 64, v)- Loads and stores on a shadow stack, which only its instructions and
the control transfers make: they raise #PF unless the page at
ais a shadow-stack page of user mode at CPL 3, of supervisor mode below it, and of user mode forss_store_user, WRUSS’s. uif,uintr_tt,uintr_misc,send_ipi(v, id)- The user-interrupt flag, which lets user interrupts in; IA32_UINTR_TT
(985H), the address of the user-interrupt target table, with bit 0
set where it is valid; IA32_UINTR_MISC (986H), whose bits 31:0 are
the table’s highest index; and an ordinary interprocessor interrupt
with vector
v, sent to the processor whose APIC ID isid. rtm_active,rtm_nest,rtm_nest_max,ldtrk_suspended,hle_active,fallback- Whether the processor runs an RTM transaction, how many XBEGINs deep, and how deep it lets them nest (its own limit); whether XSUSLDTRK keeps loads out of the transaction’s read set; whether it runs an HLE region; and where an abort goes.
tx_abort(status),tx_commit()- An abort: every register and memory write since the outermost XBEGIN
is undone, EAX gets
status, and the processor goes on atfallback; and whether the outermost XEND commits, which is the processor’s to decide: another processor may have written the transaction’s memory. iwkey,wrap_key(key, meta),unwrap_key(h)- Key Locker’s internal wrapping key, which software loads but cannot
read: the encryption key in bits 255:0, the integrity key in 383:256,
NoBackup in 384 and KeySource in 388:385; what ENCODEKEY128 and
ENCODEKEY256 make of an AES key under it with AES-GCM-SIV, the
128-bit integrity tag and, above it, the encrypted key; and the
reverse, which AESENC128KL and its kin take: the key that a handle
hholds (the metadata, then whatwrap_keymade), or -1 wherehfails the integrity test, as a handle made under another key, or changed since, does. Both results are the processor’s: the tests take them from each case rather than compute them, since a case cannot know the key, and no processor here has Key Locker to check a model of the algorithm. rtit_ctl,rtit_status,ptw_packet(v, 64, ip)- The control and status registers of Intel PT, IA32_RTIT_CTL (570H)
and IA32_RTIT_STATUS (571H), and a PTW packet that PTWRITE writes to
the trace, with
vas its payload, followed by a FUP packet with the instruction’s address whereipis 1. bnd,bnd.number- A bound register of MPX, BND0 to BND3, 128 bits: the lower bound in
bits 63:0 and the upper bound in bits 127:64, which BNDMK keeps as
its ones’ complement, so that a register of zeros allows every
address.
.numberis the number the instruction encodes, up to 15: a block refuses BND4 to BND15 (#UD). mib.address,base_reg(x),index_reg(x)- The memory operand of BNDLDX and BNDSTX is not read: its address,
the base register plus the displacement (0 without a base register),
is that of a pointer, which picks an entry of the bound tables, and
its index register holds the pointer’s value.
base_reg(x)andindex_reg(x)are the values of the base and index registers of such an operand, or of BNDMK’s, 0 for one it does not have. bndcfgu,bndcfgs,bndstatus,bound_fault(s)- MPX’s configuration at CPL 3, BNDCFGU, and below it, the MSR
IA32_BNDCFGS: bit 0 turns MPX on, bits 63:12 hold the address of the
bound directory. BNDSTATUS says why MPX last raised #BR, which
bound_fault(s)does after setting BNDSTATUS tos: of a block’s writes, that one alone outlasts the fault. With MPX off, and on every processor without it, the MPX instructions do nothing. key_loaded- Bit 30 of RFLAGS on VIA’s processors: 1 when PadLock’s AES engine holds the control word and keys of an earlier REP XCRYPT, which the next one then does not load again. Any store or load of RFLAGS clears it (PUSHF, POPF, an interrupt), and so do REP XSHA1 and REP XSHA256.
ace_load(c, k),ace_cw,ace_defined(),ace_encrypt(b)- PadLock’s AES engine.
ace_loadloads its control word from addressc: bits 3:0 the rounds (0 for 16), bit 4 every block to one place (a MAC), bit 5 data at any alignment, bit 6 the algorithm (0, AES), bit 7 keys from memory, bit 8 intermediate results, bit 9 decryption, bits 11:10 the key size; and its round keys, which the engine expands from the 128-bit key atk, or reads from there, 16 of them.ace_cwis the control word it holds, andace_defined()0 where VIA leaves the results undefined.ace_encryptandace_decryptput a block through FIPS-197’s cipher, or its equivalent inverse cipher, with the engine’s keys. rng_msr,sha1_block(h, w),sha256_block(h, w)- MSR 110B, which turns PadLock’s random number generator on (bit 6)
and whose bits 31:5 XSTORE returns; and a step of its hash engine:
the SHA-1 or SHA-256 state
h, which it keeps in memory as doublewords in the processor’s byte order, after the 64-byte blockw, whose words SHA reads big-endian. lwp_cbaddr,lwp_cfg,lwp_count[i],lwp_head,lwp_min(i)- AMD’s Lightweight Profiling: the address of the control block in
use (the MSR LWP_CBADDR, 0 while LWP is off); the features that the
operating system allows, in the bits of the control block’s Flags,
and in bits 39:32 the number of this core (the MSR LWP_CFG); the
counter of event
iand the offset in the ring buffer where the next record goes, which LWP keeps to itself while it runs and writes to the control block when asked; and the least interval that the processor allows for eventi. ptsc(),this_rip- The Performance Time Stamp Counter, the processor’s clock of 100 MHz
that LWP’s records may carry; and the address of the instruction
itself, which LWP’s records carry too:
ripis the next instruction’s,this_ripplus the instruction’s length.
The pages of virtualization (VMX, SVM, SEV-SNP, Intel TDX) and of the enclaves add the processor’s mode and the structures of a hypervisor. Their procedures are long, so their blocks name the steps, as below, with the section of the manual that lists what a step checks or loads.
in_vmx,vmx_nonroot,seam,in_smm,in_smx- 1 when the processor is in VMX operation (between VMXON and VMXOFF), in a guest (VMX non-root operation), in Intel TDX’s secure arbitration mode (SEAM, whose guests are trust domains), in system-management mode, and in SMX operation (after GETSEC[SENTER]); else 0. A Linux process, where the probe runs, is in none of them.
dual_monitor,mov_ss- 1 when the dual-monitor treatment of SMIs and SMM is active, and when the instruction comes right after a MOV to SS or a POP of SS, which blocks events for one instruction.
current_vmcs,vmxon_ptr,NO_VMCS,maxphyaddr- The physical addresses of the current VMCS, the structure that
describes a guest, and of the region that VMXON took;
NO_VMCS, all ones, when there is no current VMCS.maxphyaddris the width of physical addresses, which the instructions check addresses against. phys_read(a, 32),phys_write(a, 64, v)- Memory at a physical address, which the structures of a hypervisor use and no linear address reaches; here 32 and 64 bits of it.
vmcs_read(p, f),vmcs_write(p, f, v),vmcs_has(f)- Field
fof the VMCS atp, by the encoding that VMREAD takes, whose bits 14:13 give its width (16, 64, 32 bits or the natural width) and whose bit 0 picks bits 63:32 of a 64-bit field; and whether the processor has the field. The processor keeps a VMCS’s data in a format of its own, so the fields are named, not placed. launched(p),vmcs_clear(p),set_launched(p)- The launch state of a VMCS, 1 after VMLAUNCH, 0 after VMCLEAR, which makes it clear and has the processor write its copy of the VMCS’s data to the region.
IA32_VMX_BASIC,IA32_FEATURE_CONTROL- The numbers of model-specific registers, which
msr[...]reads, under their names in the manuals: the VMX capability registers say what the processor supports, such as the VMCS revision identifier in bits 30:0 of IA32_VMX_BASIC. vm_succeed(),vm_fail(n),vm_fail_invalid()- How a VMX instruction reports its outcome: success clears CF, PF,
AF, ZF, SF and OF; a failure with a current VMCS sets ZF and writes
error number
ninto the VMCS’s VM-instruction error field, and one without sets CF (Volume 3, 33.2 and 33.4 of Intel’s SDM). vm_exit(21)- The instruction, run in a guest, hands control to the hypervisor with a VM exit of that basic reason (here VMPTRLD’s), and an exit qualification where the block gives one. The tests stop there, as the guest does.
controls_ok(),host_state_ok(),guest_state_ok(),msr_load_ok()- Whether a VM entry passes the checks of the VMX controls (29.2.1), of the host-state area (29.2.2 and 29.2.3) and of the guest-state area (29.3.1), and loads the MSRs of the VM-entry MSR-load area (29.4). A processor makes these hundreds of checks in an order of its own, so the tests take their outcome from the case.
load_guest(),entry_fail(33)- A VM entry loads the guest-state area of the current VMCS (29.3.2): CR0, CR3, CR4, DR7, RSP, RIP, RFLAGS, the segment registers with their hidden parts, GDTR, IDTR and the MSRs the controls name; CPL becomes the DPL of the guest’s SS. A VM entry that fails after its first checks (29.8) records the exit reason, with bit 31 set, and loads the host-state area instead, as a VM exit does (30.5), RFLAGS cleared but bit 1.
exit_controls_ok(),eptp_ok(v)- Whether the VM-exit controls pass the checks VMCALL makes before it
activates the dual-monitor treatment (34.15.6.1), and whether
vis an EPT pointer a VM entry accepts (29.2.1.1): a memory type and page walk that IA32_VMX_EPT_VPID_CAP allows, no reserved bit set. gif,intercepted(0x80),vm_exit(0x80)- AMD’s global interrupt flag, which STGI sets and CLGI clears; and, in an SVM guest, whether its hypervisor intercepts the event of that exit code, here VMRUN’s, which then ends the instruction with that #VMEXIT.
save_host(a),vmcb_ok(),set_rflags(v),set_cpl(n)- VMRUN saves the host’s state for the #VMEXIT that returns to it, in a format of the processor’s, at the address that VM_HSAVE_PA gives; checks the guest’s state in the VMCB (15.5.1 of AMD’s APM, Volume 2, whose outcome the tests take from the case); and loads RFLAGS and CPL, with the rest of the guest’s state from the VMCB’s offsets.
vmcb_save_segments(a),vmcb_load_segments(a),init_state()- FS, GS, LDTR and TR with the attributes, limit and base that their descriptors loaded, 16 bytes each at 440H, 450H, 470H and 490H of the VMCB; and the state that an INIT signal leaves, from which SKINIT starts the secure loader.
snp_active,asid,vmpl- 1 in an SNP-active guest of SEV-SNP; the ASID of the guest that runs, 0 in the hypervisor; and its VM permission level, 0 the most privileged.
guest_pa(va),system_pa(gpa),npt_large(gpa)- The guest physical address of a virtual one, by the guest’s page tables (#PF where they map none), and the system physical address of that, by the hypervisor’s nested page tables, which may map it in a 2-MB page (#VMEXIT(NPF), 400H, where they map none).
rmp(spa),set_rmp(spa, v),in_rmp(spa)- The entry of a page in SEV-SNP’s reverse map table, whose format the APM leaves to the processor, as a number of the model’s: bits 63:0 the guest physical address, 64 Assigned, 72 a 2-MB page, 80 Immutable, 127:96 the ASID (the layout RMPREAD stores), 128 Validated, 129 VMSA, 130 Not-Dirty, then a permission mask of 8 bits for each VMPL from bit 136 up; and whether the table, from RMP_BASE to RMP_END, has an entry for the page.
seam_loader,seam_ready_ok(),seam_call(loader)- Intel TDX’s module runs in SEAM root operation, as its loader where
seam_loaderis 1. SEAMCALL enters it where it is ready, and a SEAM call works as an SMM VM exit: the hypervisor’s state is saved in the SEAM-transfer VMCS, which becomes current, and the module’s loaded. leaf_exists(n),leaf_function(n)- GETSEC, ENCLS, ENCLU, ENCLV, SEAMOPS and PCONFIG run the leaf
function that EAX selects, which the manuals describe leaf by leaf:
whether the processor has leaf
n, and the leaf’s work, which returns the code it reports, 0 for success. The tests take what a leaf writes from the case. smx_capabilities(i),seamops_capabilities(),pconfig_target(t)- The processor’s answers: what GETSEC[CAPABILITIES] gives for index
i, the bitmap of the SEAMOPS leaves it has, and whether CPUID leaf 1BH lists PCONFIG’s targett, 1 for TME-MK and 2 for TSE. enclave_mode,VC- 1 while the processor runs in an SGX enclave; and the VMM communication exception, #VC, of SEV’s guests.
Values are integers of any size, and registers and memory read as
unsigned numbers; a write keeps the low bits, so that -1 is all ones.
Inside a block, registers and flags keep their values from before the
instruction, and the writes take effect in order at its end: when an
operand names the same register as another, as in XADD EAX, EAX, both
read the old value, and the last write stays. So that this never
matters to a reader, no block reads a register after writing it.
The blocks of the vector pages are written from the model that draws their data-flow diagrams, and add these:
zmm1,zmm2,src3,mem- The operands by their place in the syntax, each named after the
widest register the block’s forms have there:
zmm1is xmm1, ymm1 or zmm1, whichever the form uses, andmm1an MMX register. An operand that is a register in some forms and memory in others issrc2orsrc3(destin the first place); one always in memory ismem.k1andk2are mask registers. .b,.w,.d,.q,.dq,.qq- An operand as an array of 8-, 16-, 32-, 64-, 128- or 256-bit
elements, counted from bit 0:
zmm2.d[3]is bits 127:96..sb,.sw,.sdand.sqread the same bits as signed numbers. In memory,.d[i]is 4i bytes from the operand’s address. k1[i],zeroing- Bit i of the write mask: whether element i is written. It is 1 for
every element in a form without a mask. An element masked off keeps
its value, or becomes 0 in a
{z}form, wherezeroingis true; it is not read from memory either, which is why the reads sit insideif k1[i]:. k1.group[1],zmm2.group[j]- The registers in a row that one operand stands for, which the syntax
writes with a
+:k1+1is a pair of mask registers,zmm2+3four vector registers. The group starts at the encoded register’s number with its low bit, or its low two bits, cleared, so thatk1.group[0]is the even register of the pair andk1.group[1]the odd one after it, andzmm2.group[j]is register j of the four. VL- The vector length of the form in bits: 128, 256 or 512, and 64 for
MMX. A block for several lengths counts its elements as
VL // 32. m32bcst- A broadcast: one doubleword in memory stands for every element, so
that
src3.d[i]is that doubleword for every i. mem.base,mem.index,mem.scale,load(a, 32)- The memory operand of a gather or scatter: a base address, a vector
register of signed offsets and the scale they are multiplied by.
load(a, 32)reads the 32 bits at address a, andstore(a, 32, v)writes them when the instruction ends, in order, so that the last of two stores to one address stays.k1.write(0)clears the whole mask register, as gathers and scatters do. src1 = xmm1.read()- A copy of a register as it was before the instruction, for a legacy
form whose destination is a source too: the block writes
xmm1and reads the old elements fromsrc1. Memory that a block writes element by element is written at its end, too: a vector instruction that faults, as on an unmasked exception (#XM), leaves registers and memory as they were. ssat(x, 16),usat(x, 8)xsaturated to the signed or unsigned range of that many bits. The other helpers of the element operations, such asrol,popcountandternlog, are named after what they compute.sub_bytes(s),shift_rows(s),mix_columns(s),sub_word(w)- The steps of an AES round as FIPS-197 defines them, on a 128-bit
state
swhose byte j is in row j % 4 of column j // 4: every byte through the S-box; row r turned left by r bytes; every column taken as a polynomial over GF(2^8) and multiplied by 3x^3 + x^2 + x + 2, modulo x^4 + 1. Withinv_in front, as ininv_mix_columns(s), a step is undone.sub_word(w)puts the four bytes of a doubleword through the S-box, as the key expansion’s SubWord does. aes_encrypt(s, k, 128),aes_decrypt(s, k, 256)- The whole cipher, every round of it: the 128-bit block
sencrypted or decrypted under the keykof that many bits, 10 rounds for AES-128 and 14 for AES-256, with the round keys of FIPS-197’s key expansion. The key’s bytes are in the order of memory, as an XMM register holds them. gf2p8inv(x)- The inverse of the byte
xin GF(2^8), the field of AES and GFNI, whose bytes are polynomials modulo x^8 + x^4 + x^3 + x + 1; 0 for 0. The S-box takes a byte to its inverse, then through an affine map. choose(x, y, z),majority(x, y, z)- The bitwise functions of SHA that FIPS 180-4 calls Ch and Maj: each
bit of
ywherexhas a 1 and ofzwhere it has a 0; and the majority of the three bits. SHA-1 takes them in rounds 0 to 19 and 40 to 59, SM3 from round 16 on. sum0(x, 32),sum1,sigma0,sigma1- The functions that FIPS 180-4 writes with a sigma, upper case for
the rounds and lower case for the message schedule, on words of 32
bits (SHA-256) or 64 (SHA-512):
xturned right by three amounts, or by two and shifted right by a third, the three added (exclusive or). SHA-256’s turn by 2, 13 and 22 (sum0), 6, 11 and 25 (sum1), 7 and 18 and shift by 3 (sigma0), 17 and 19 and shift by 10 (sigma1); SHA-512’s by 28, 34 and 39; 14, 18 and 41; 1, 8 and 7; 19, 61 and 6. sm3_p0(x),sm3_p1(x)- SM3’s permutations P0 and P1 (GB/T 32905):
x ^ rol(x, 9, 32) ^ rol(x, 17, 32), and the same with 15 and 23. sm4_sub_word(x),sm4_l(x),sm4_l_key(x)- SM4’s steps (GB/T 32907): each byte of the doubleword
xthrough its S-box, which takes a byte through an affine map, to its inverse in GF(2^8) modulo x^8 + x^7 + x^6 + x^5 + x^4 + x^2 + 1, and through the affine map again; and its linear maps,xandxturned left by 2, 10, 18 and 24 bits, added, in the rounds, and by 13 and 23 in the key expansion. hmac_sha256(k, m, n),gcm_encrypt(k, iv, p, n),gcm_tag(k, iv, a, na, c, nc)- The cryptography of PBNDKB: an HMAC (RFC 2104) with SHA-256 of
nbytes ofmunder the 32-byte keyk; and AES-256 in Galois/Counter Mode (NIST SP 800-38D), which encryptsnbytes ofpunder the keykwith the 12-byte IViv, and authenticatesnabytes ofaand thencbytes of the ciphertextcwith a 16-byte tag. Keys, data and results are bytes in the order of memory, asloadreads them. platform_key- A 256-bit key that the processor keeps to itself and no instruction reads, from which PBNDKB derives the key it encrypts with.
The last line of a block says what happens to the destination register above the bits the form writes: a VEX or EVEX form zeroes them, a legacy SSE form leaves them as they were, and an MMX form changes the x87 state that its register shares.
Floating-point elements are numbers, which these helpers compute with:
.f32,.f64,.f16,.bf16- An operand’s elements as single, double, half and bfloat16 numbers.
An instruction that only moves them uses
.dor.q, their bits. add(a, b),sub,mul,div,sqrt(a)- The exact result, rounded once to the format of the elements: as
MXCSR.RC says, or as the form’s
{er}does. fmin(a, b),fmax(a, b)- The smaller or larger of the two, as MINPS and MAXPS pick it:
bwhen either is a NaN or both are zeros. fmadd(a, b, c),fmsub,fnmadd,fnmsuba * b + c,a * b - c,-(a * b) + cand-(a * b) - c, rounded once.fcmp(imm8, a, b),comi(a, b),ucomi(a, b)- A compare by the predicate imm8 & 31 of CMPPS, true or false; and the order of COMISS and UCOMISS: 0 greater, 1 less, 2 equal and 3 unordered.
to_f32(x),cvt_int(a, 32),cvtt_int(a, 32)- Conversions: from an element of another format or an integer; to a
32-bit integer, rounded or truncated, or the integer indefinite (the
smallest signed integer) where the value does not fit.
cvt_uintconverts to an unsigned integer, all ones where it does not fit.to_f16(a, imm8)rounds as imm8 says, andto_bf16_ne(a)as the BF16 instructions do: to nearest even, denormals flushed to zero, no flags, which is also howfmadd_ne(a, b, c)roundsatimesbplus the singlec, for bfloat16 elements or, in VDPPHPS, half ones, whose denormals it keeps.to_f32_ne(a)converts a half or bfloat16 element exactly, with no flags, andto_f32_f16c(a)a half as VCVTPH2PS does: exactly, a denormal kept whatever DAZ says and without DE, an SNaN quieted with IE. to_bf8(a),to_hf8(a),to_hf8s(a)- Conversions to AVX10.2’s 8-bit formats, E5M2 (
.bf8, with the infinities and NaNs of IEEE 754) and E4M3 (.hf8, largest 448, no infinity and a single NaN of each sign, all ones): to nearest even, denormals kept. What does not fit after rounding, or an infinity, is E5M2’s infinity or E4M3’s NaN;to_bf8sandto_hf8ssaturate instead, to the largest number of its sign, andto_hf8_oddrounds to odd (ACE’s VCVTROPS2HF8), a denormal single being a zero.to_bf4s(a)converts to the 4-bit E2M1 (.bf4, two to a byte), which has neither infinity nor NaN: what does not fit, and a NaN, is its largest number, 6, of its sign;to_bf6s(a)andto_hf6s(a)convert likewise to ACE’s 6-bit E3M2 (.bf6, largest 28) and E2M3 (.hf6, largest 7.5), whose element i is bits 6i+5:6i, packed with no gaps. These conversions, and those from the 8-, 6- and 4-bit formats, which are exact, leave MXCSR unused and set no flags. round(a, imm8),rndscale(a, imm8),reduce(a, imm8)arounded to an integral value, by the rounding imm8 names; to imm8[7:4] bits of fraction; and what that rounding leaves over,aless the rounded value.getexp(a),scalef(a, b),fpclass(imm8, a)- The exponent of
a, floor(log2(|a|)), as a number;atimes 2 to the power floor(b), rounded; and whetherais of one of the classes imm8 selects: bit 0 QNaN, 1 +0, 2 -0, 3 +inf, 4 -inf, 5 denormal, 6 negative and finite, 7 SNaN. getmant(a, imm8),frange(a, b, imm8),fixupimm(a, b, sc, imm8)- The significand of
a, scaled into the interval imm8[1:0] names; the smaller or larger ofaandb, or of their magnitudes, with the sign that imm8[3:2] picks (VRANGEPS); and VFIXUPIMMPS’s fix-up, where the tablescnames for the class ofb(NaN, zero, +1, an infinity, a negative or positive number) what the result is,aitself among the choices. fminmax(a, b, imm8),comx(a, b),cvts_int(a, 8),cvtts_int(a, 32)- AVX10.2’s minimum and maximum of IEEE 754-2019, in the form imm8 selects, with the sign imm8[3:2] picks; COMISS’s compare, whose result VCOMXSS turns into the flags of a signed compare as well; and conversions to integers, rounded or truncated, that saturate: the nearest integer that fits, 0 for a NaN.
rcp(a),rsqrt(a),rcp14(a),rsqrt14(a),rcp28(a),exp2(a)- Estimates of 1/a, 1/sqrt(a) and 2^a, whose last bits differ between processors: RCPPS and RSQRTPS (and VRCPPH, VRCPBF16 for their formats), VRCP14PS, AVX512ER’s VRCP28PS and VEXP2PS. The block gives the exact value, and the tests take any result within the relative error that the manuals allow, which the block states: 1.5 * 2^-12 for RCPPS, 2^-14 for VRCP14PS. Beside it are the number of the page’s results recorded on Zen 5 and the worst error among them, which a test holds to the cases. A result too small for a normal number may be a zero where the instruction flushes one, as RCPPS always does. Zeros, infinities, NaNs and the roots of negative numbers give exact results, and only the AVX512ER estimates raise exceptions.
NaNs, denormals and exceptions follow the SSE rules, with MXCSR’s DAZ
and FTZ. An element’s exceptions are flagged once every element is
computed: an unmasked one raises #XM and the instruction writes nothing,
masked ones set their MXCSR flags. {er} and {sae} suppress them,
and the complex FP16 multiplies act as if all of them were masked, as
the SDM says; no processor here has AVX512-FP16 to check that.
Arithmetic on BF16 elements (.bf16) follows the rule of the BF16
instructions instead: it rounds to nearest even, treats denormals as
zeros and flushes denormal results, sets no flags and ignores MXCSR.
AMD’s 3DNow! pages compute with two singles in an MMX register, and
their helpers keep their names but follow 3DNow!’s rules, as AMD’s
manuals give them. An exponent of 0 is a zero, whatever the fraction,
so there are no denormals; an exponent of 255 is unsupported, and an
operation on it is UNDEFINED, but where AMD’s table for the
instruction says otherwise, as a zero plus such an element gives the
element. Results round to nearest, even on a tie; an exact result
smaller than 2^-126 is a zero, and one of 2^128 or more after rounding
is the largest number, as there are no infinities or NaNs. A sum that
is exactly zero takes the sign of its first term, and a sum of two
zeros is negative only when both are. Nothing raises an exception or
touches MXCSR. No processor here has 3DNow!, so these blocks rest on
AMD’s documents and on cases worked out by hand.
add(a, b),sub,mul,fmin,fmax,comi(a, b),is_unsupported(x)- The arithmetic as above;
fminandfmaxtake a zero as +0 and return +0 for one;comigives 0 greater, 1 less, 2 equal (any two zeros are) and 3 where an element has an exponent of 255, whichis_unsupportedtests. cvtts_int(a, 32),to_f32(n)- PF2ID’s and PF2IW’s conversion to an integer: truncated, and saturated to 32 or 16 bits. PI2FD’s from an integer: truncated, not rounded.
rcp(a),rsqrt(a)- PFRCP’s and PFRSQRT’s estimates: 1/a within 2^-14, and 1/sqrt(|a|)
with the sign of
awithin 2^-15, the bounds that AMD gives. The estimate of a zero is the largest number of its sign. rcp_step(a, b),rsqrt_step(a, b),refine(t, x)- The two steps of Newton-Raphson that bring an estimate x of 1/b or
1/sqrt(b) to 24 bits. PFRCPIT1 computes 2 - b * x (
rcp_step), PFRSQIT1 (3 - b * x * x) / 2 from b and the square of x (rsqrt_step), each to 32 bits and packed into an element in a form that only PFRCPIT2 reads: the eight bits after the integer bit, which are all equal when x is close to its target, are left out. PFRCPIT2 (refine) puts them back and multiplies by x. AMD rounds that product after a correction it does not describe, so the tests take any single within one unit in the last place of the exact product.
The x87 pages add the floating-point unit: its stack of eight registers, each holding an 80-bit double extended number with an explicit integer bit, and its words.
st0…st7,st[i]- The registers of the stack, ST(0) to ST(7), counted from the top as
it was before the instruction. An ST(i) of the syntax is an operand
like any other,
destorsrc. push(v),pop()- A push writes
vbelow the top and makes it the top; a pop frees ST(0) and moves the top up one. Like every write they take effect at the end of the block, sost1keeps naming the register that was ST(1): what a block assigns tost0before a push ends up in ST(1). empty(r),free(r)- Whether a register is tagged empty, and tagging it so, as FFREE does. The value stays in the register.
underflow(),overflow()- A stack fault: a register operand that is empty, or a push onto a
full stack. Both set IE and SF, with C1 = 0 for an underflow and 1 for
an overflow. What follows with IE masked is the block’s own code,
usually a write of
INDEFINITE, the QNaN floating-point indefinite. top,fcw,fsw,ftw- TOP, and the control, status and tag words. ES and B of the status word are set exactly when an exception flag is set whose mask is clear. The tag word reads as FNSTENV stores it, each register’s tag worked out from its contents.
fip,fcs,fop,fdp,fds- Where the last x87 instruction that was not a control instruction was: its offset and code segment, its opcode, and the offset and segment of its memory operand, which FNSTENV and FNSAVE store and FLDENV and FRSTOR load.
c0…c3,ie,de,ze,oe,ue,pe,stack_fault- The condition codes, the exception flags and SF (
sfis the flag of RFLAGS). The exceptions that the helpers raise are not assigned. The tests hold the condition codes to XED’s records, which say only whether an instruction changes a code or leaves it undefined: a block that clears one, such as FABS’s C1, meets “changed”. add(a, b),sub,mul,div,sqrt(a)- The same names as in the vector blocks, with the same meaning: the
exact result, rounded once. The vector blocks round by MXCSR; the x87
blocks round by PC (to 24, 53 or 64 bits of significand, the exponent
keeping the registers’ range) and RC of the control word. C1 becomes 1
when the rounding increased the magnitude, and 0 otherwise. A memory
operand is a number of its width (m32fp a single, m64fp a double), and
an integer, such as FIADD’s
signed(src), is its exact value. to_f80(x),to_f32(x),cvt_int(x, 16),to_bcd(x),from_bcd(v)- Conversions. A load is exact. A store to a single (
to_f32) or a double (to_f64) rounds by RC, not PC. A store to an integer rounds by RC, or toward zero (cvtt_int, FISTTP); a value that does not fit gives the integer indefinite, the smallest integer.to_bcdrounds to 18 decimal digits, as FBSTP stores them, andfrom_bcdreads them. comi(a, b),ucomi(a, b),is_nan(x)- FCOM’s and FUCOM’s compare: 0 greater, 1 less, 2 equal, 3 unordered.
Both raise IE for an encoding that the 387 dropped; for a NaN,
comiraises it for any anducomifor an SNaN only.is_nan,is_snan,is_inf,is_zero,is_denormal,is_finiteandis_unsupportedgive a number’s class;is_snantells a signaling NaN from a quiet one. less(a, b),abs(x)- Whether the number
ais less thanb(not if either is a NaN), andxwith its sign bit cleared, as FABS does; they raise nothing. round(x),scale(a, b),exponent(x),significand(x)xrounded to an integer by RC (FRNDINT);atimes 2 to the power ofbtruncated toward zero (FSCALE); and the two parts FXTRACT splitsxinto, its exponent as a number andxwith its exponent made 0.prem(a, b),prem1(a, b),r.quotient,r.partial- The remainder of
abybless a whole numberqof timesb, exact,qtruncated (FPREM) or rounded to the nearest integer, even on a tie (FPREM1)..quotientisqwithout its sign, whose low bits go to C0, C3 and C1;.partialis 1 where the exponents ofaandbare 64 or more apart, and one step reduces the exponent by 32 to 63 only. sin(x),cos,tan,atan2(y, x),exp2m1(x),ylog2(y, x),ylog2p1(y, x)- The functions of the transcendental instructions: the sine, cosine and tangent, the angle of the point (x, y), 2^x - 1, y * log2(x) and y * log2(x + 1), each rounded once by RC to 64 bits, whatever PC says. They raise PE for every result they compute, even an exact one. The sine, cosine and tangent are of x * pi / Pi, where Pi is the 66-bit approximation of pi by which the processor reduces the argument: near a multiple of pi / 2 the results are those of a slightly different angle.
These exceptions exist:
- IE: an SNaN operand, an encoding that the 387 dropped (unnormals, pseudo-NaNs and pseudo-infinities), or an invalid operation such as zero times infinity;
- DE: a denormal operand;
- ZE: a division by zero;
- OE, UE and PE: a rounded result too large, tiny, or inexact.
A masked exception only sets its flag. An unmasked one also sets ES and B, and the next waiting instruction raises #MF, as the cases record it. The two kinds of unmasked exception end differently:
- detected before the operation (IE, a stack fault, DE or ZE): the operation stops at the helper that detects it. Whatever the block writes after that call to registers, TOP or memory does not happen, so a result is not written and a pop does not pop. The status is written all the same: the flags, the condition codes (FCOM’s unordered) and RFLAGS (FCOMI’s). A helper that stops rounds nothing, so the C1 it sets is 0. A load’s DE is the exception to this rule: Zen 5 loads the denormal all the same;
- an overflow or underflow into a register: the result is written with its exponent brought into range by 2^24576. Into memory, nothing is written.
A waiting instruction that begins with an exception pending raises #MF before anything else.
The transcendental instructions are approximations whose last bit differs between processors. Their pseudocode gives the exact value rounded once, and the tests take any result a processor records within 1 ulp of the exact value when rounding to nearest, 1.5 ulps in the other modes: the bounds that Intel’s manual gives. C1 says which way the processor rounded its own approximation, so it may say either where the result lies within a quarter of an ulp of the exact value.
The AMX and ACE pages add the tiles: eight registers of up to 16 rows of 64 bytes, and TILECFG, which gives each its shape. Under palette 1, AMX’s, each tile has the rows and the bytes per row that LDTILECFG loaded; under palette 2, ACE’s, every tile has all 16 rows of 64 bytes. No processor here has either, so these blocks were not run.
tmm1,tmm2,tmm[i]- The tiles of the syntax, by their place in it, as the vector operands
are named, and tile
iby number. tmm1.rows,tmm1.colsb- The rows of a tile and the bytes in each of its rows: 0 and 0 for a tile that the configuration leaves out, which is not valid.
tmm1.row[r],tmm1.row[m].f32[n]- Row
rof a tile, 512 bits, and its elements, with the views of the vector pages. A write lands when the instruction ends; the tile is then zeroed past its rows, and each row written past its bytes per row, as the block’s last line says. tilecfg,palette,start_row- TILECFG as the 64 bytes that STTILECFG stores: the palette in byte 0,
start_rowin byte 1, then each tile’s bytes per row (bytes 16 + 2n) and rows (byte 48 + n). Palette 0 means no configuration is loaded;start_rowis where an interrupted TILELOADD or TILESTORED goes on. palettes,xfd- The palettes the processor has, bit p for palette p, and IA32_XFD, whose bit 18 lets the operating system keep the tiles from a thread (#NM).
bsr0- ACE’s block scale register: 128 scales of a byte each, the A scales of the rows in bytes 64 to 127 and the B scales of the columns in bytes 0 to 63. A scale e stands for 2^(e - 127); FFH is a NaN.
mem.address,mem.stride- Where row 0 of TILELOADD’s or TILESTORED’s memory is (base plus displacement), and the distance between rows (the index register times the scale, 0 without one).
add_ne(a, b),neg(x)- The sum of two singles, rounded to nearest even with denormals
flushed in and out and no flags, as
fmadd_nerounds; andxwith its sign flipped. mul_exact(a, b),add_exact(x, y),round_ftz(x, e)- Exact products and sums of elements, and an exact value times 2^e rounded once to a single, to nearest even. BF16 and single denormals are zeros, FP16 and FP8 ones numbers. Any NaN, zero times an infinity, and infinities of both signs give the QNaN indefinite, FFC00000H; a result too small for a normal single is a zero, one too large an infinity.
to_f16_ne(a),cvt_f32_ne(x)- A single converted to FP16, to nearest even, a single denormal taken as zero, FP16 denormals kept; an integer converted to a single, to nearest even. Neither uses MXCSR or sets a flag.
Operands
Each page lists what its forms read and write, as XED records it.
Explicit operands are those of the syntax, in its order; implicit ones
are fixed by the opcode and left out of the syntax, such as the
accumulator of CMPXCHG, the flags register or the stack. Forms that
differ only in operand size or vector length share a block, which
gives each operand’s sizes (r8/16/32/64) or registers
(xmm, ymm, zmm).
r/m8,xmm/m128- A register form and a memory form that are otherwise the same, written as one, as in Intel’s manuals.
- read, write
- The form reads the operand, writes it, or both.
- conditional write, conditional read
- The form writes or reads the operand only in some cases: CMPXCHG loads the accumulator only when the comparison fails, and a REP string instruction with a count of 0 touches no memory.
- (masked),
{k} - An EVEX destination written under an opmask register, and the opmask
itself. Elements that the mask leaves out keep their value (the
destination is then read as well) or, with
{z}, are cleared. The blend instructions such as VBLENDMPS use the opmask as a selector instead: it picks each element from one source or the other. - push, pop, pop twice
- The form pushes a value onto the x87 register stack or pops one or two off it, which moves its top.
- address only
- Only the address of the memory operand is computed; no memory is accessed, as in LEA.
stack,rSP- A push writes below the stack pointer and a pop reads at it; both move it.
m8 at ES:[rDI]- Memory that the form addresses with the registers in brackets, as the string instructions do. ES is fixed; DS, the default, is not written, since a segment prefix can replace it.
- (NF=0)
- An APX form with optional NF writes the flags only with NF=0.
Flags
The table has a column for each flag that a form tests or changes: the status flags OF, SF, ZF, AF, PF and CF, other flags of RFLAGS where a form affects them, and the condition codes C0 to C3 of the x87 status word.
T- Tested: the form reads the flag, as a conditional jump does.
M- Modified: set or cleared according to the result.
0,1- Cleared or set, whatever the result.
U- Undefined: the form changes the flag, but its value must not be relied on.
P,A- Loaded from the stack (POPF, IRET) or from AH (SAHF).
TM- Tested, then modified, as ADC and RCL do with CF.
When a form affects the flags in more than one way, the When column says in which case. For a shift or rotate by an immediate, it is a count of 1 or of 2 or more, since OF is defined only for a count of 1, and a count of 0 changes no flag; the count is what the processor leaves of it after masking it to 5 bits (6 with a 64-bit operand). For an APX form with optional NF, it is NF=0, and on a page of several conditions such as CMOVcc, each condition, whose flags the form tests. “In some cases” means that the form may leave the flags unchanged, as a shift by CL does when the count is 0.
Where Intel’s documentation says otherwise than XED about the flags of an instruction, a note under the table, or under the line that says XED records no flags, points out how, while the section keeps XED’s data.
Exception class
The exception class is XED’s name for the set of exception conditions that a form follows: which exceptions it can raise, such as #UD, #GP or #PF, and when, in each processor mode. Most names follow the exception types of Intel’s manuals: SSE_TYPE_2 is Exceptions Type 2 for SSE instructions, avx-type-2 the same type for their VEX forms, and AVX512-E2 the EVEX class E2. Other extensions, such as AMX and APX, have classes of their own. Most general-purpose instructions have none in XED.
Each class links to a page of its own, which lists its exceptions by processor mode, with what raises each, and the instructions that XED puts in the class. The exception classes index lists them all.
Attributes
Of XED’s attributes of a form, the pages show those that the rest of the page does not say.
- privileged: CPL 0 only
- The form runs only at the highest privilege level, as in an operating system kernel.
- not in real-address mode
- The form is invalid in real-address mode, as protected-mode instructions such as LTR are.
- accepts a LOCK prefix
- The memory form can take a LOCK prefix, which makes its read-modify-write atomic; the forms with LOCK are listed separately.
- locked: atomic read-modify-write
- The form is atomic: it has a LOCK prefix, or is XCHG with memory, which is always locked.
- always atomic
- The form is atomic without a LOCK prefix, as AADD is.
- accepts XACQUIRE, accepts XRELEASE
- The form can take a hint prefix of hardware lock elision (HLE).
- repeated: count in rCX
- A REP form: the operation repeats, counting rCX down to zero; REPE and REPNE also stop on ZF.
- aligned memory operand
- The memory operand must be aligned, or the form raises an exception: to 16 bytes for 128-bit SSE operands and FXSAVE, to the operand’s size for VMOVAPS and the non-temporal loads and stores, and to 64 bytes for XSAVE and MOVDIR64B.
- 4-byte aligned memory operand, 8-byte aligned memory operand
- XED marks the memory operand as needing natural alignment, by operand size: for AADD and the other RAO-INT instructions, which raise #GP when it is misaligned, and for CMPccXADD, for which Intel’s manual gives no such rule (its page says more).
- non-temporal hint
- The data is not expected to be used again soon, so the processor may bypass the caches.
- memory operand only names cache lines
- A prefetch or cache-line instruction: the memory operand selects the cache lines to act on, and no data reaches a register.
- gather, scatter
- The form loads or stores each element at its own address, from a
vector of indices (
vm32x). - write masking
- The EVEX form can be masked by an opmask register, k1 to k7.
- opmask selects the source
- The opmask is no write mask but chooses the source of each element, as in VBLENDMPS.
- embedded broadcast (tuple Full)
- The memory form can load one element and use it in every position
(
m32bcst). The tuple type, Full, Half or Quarter, sets how an 8-bit displacement is scaled. - memory fault suppression
- Elements that the mask leaves out raise no memory fault; CFCMOVcc raises none when its condition is false.
- follows MXCSR
- MXCSR’s rounding control and exception masks apply to the form, and
the floating-point exceptions that occur set its flags; a form with
{er}or{sae}can override the rounding or suppress the exceptions. - always rounds to nearest even, denormal inputs read as zero, denormal results flushed to zero
- The form rounds, or handles denormal numbers, in this way whatever MXCSR says. XED also marks the conversions of AVX10_V2_AUX to and from the 8-, 6- and 4-bit formats, and VCVTHF82PH, as flushing denormal results to zero, where ACE’s specification says that they keep them, as FTZ is not obeyed; their pages follow ACE and leave the attribute out. XED marks VDPPHPS as reading denormal inputs as zero, where AVX10.2 says so only of the single-precision accumulator and keeps the denormals of the FP16 sources; its page leaves that attribute out and keeps the flush of denormal results.
- far transfer, indirect branch
- The branch loads CS as well as rIP, or takes its target from a register or memory.
- may abort a TSX transaction
- Inside a transactional region of Intel TSX, the form may abort the transaction, on some processors or on all; “in some cases” depends on its operands, as CLD and STD abort only when they change DF.