AAA instruction (General-purpose)

AAA corrects AL after an ADD of two unpacked BCD digits, one digit to a byte. When the low four bits of AL are above 9, or AF says that the addition carried out of them, it adds 6 to AL and 1 to AH, sets AF and CF, and leaves the digit in AL; otherwise it clears AF and CF. Either way the high four bits of AL are cleared. Because those bits are ignored, ASCII digits, 30h to 39h, need no masking first: an ADD of ‘7’ and ‘5’ (37h and 35h) leaves 6Ch, and AAA with AH = 0 gives AX = 0102h, the digits 1 and 2, with CF set. An OR of AX with 3030h makes them ASCII again. OF, SF, ZF and PF are undefined.

Its kin are AAS for subtraction, AAM after a multiplication and AAD before a division. Packed BCD, two digits to a byte, has DAA and DAS instead.

A carry out of AL

Intel’s pseudocode adds 106h to AX, so a carry out of AL + 6 reaches AH as well: AL = FAh to FFh gives AH 2 more. AMD’s Volume 3 says that AH is incremented and 6 added to AL, without saying where such a carry goes. The Operation section follows Intel. The case cannot follow an ADD of two digits, even ASCII ones, whose sum is at most 72h.

Not in 64-bit mode

Opcode 37 raises #UD in 64-bit mode, so the fixture has no case for AAA: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse aaa in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. AMD’s Zen 5 guide lists AAA as microcoded, without a latency.

Forms

Every encoding of AAA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AAA` not in 64-bit mode AAA	`37`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = ax
if (a & 0xF) > 9 or af:          # the low digit overflowed
    a += 0x106                   # AL + 6, its carry into AH, and AH + 1
    af = cf = 1
else:
    af = cf = 0
ax = a & 0xFF0F                  # AL keeps its low four bits
of = sf = zf = pf = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AAA` not in 64-bit mode
`AL`	implicit	read, write
`AH`	implicit	read, write
`RFLAGS`	implicit	read, write

Flags

T tested, M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	U	U	TM	U	M

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

A carry out of AL#

Not in 64-bit mode#