AAD instruction (General-purpose)

AAD joins two unpacked BCD digits, the high one in AH and the low one in AL, into a binary number: AL becomes AL plus AH times the base, kept to 8 bits, and AH is cleared. The base is 10 unless the immediate byte says otherwise. With AX = 0708h, the digits 7 and 8, AAD gives AX = 004Eh, 78, which a DIV by an unpacked digit then divides into a quotient digit in AL and a remainder in AH, the step that long division of a BCD number by one digit repeats. SF, ZF and PF follow the new AL; OF, AF and CF are undefined.

Where AAM fixes up after the operation, AAD runs before it, since DIV needs a binary dividend; the two are inverses for values below the square of the base. Like AAM’s, the base is the second byte of the instruction, D5 0A for plain AAD: both manuals say that other bases are coded by hand, while GNU as 2.44 and Clang 23 take aad $8 in AT&T syntax. Unlike AAM, AAD has no division, so a base of 0 raises nothing: AL stays and AH is cleared.

Not in 64-bit mode

Opcode D5 raises #UD in 64-bit mode, so the fixture has no case for AAD: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse aad in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. In our builds with -m32, (ax >> 8) * 10 + (ax & 0xff) compiles at -O2 to LEA and SHR in GCC 14 and Clang 23, and at -Os to an IMUL in GCC 14. AMD’s Zen 5 guide lists AAD as microcoded, without a latency.

Forms

Every encoding of AAD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AAD imm8` not in 64-bit mode AAD_IMMb	`D5 ib`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = (al + ah * base) & 0xFF      # base is 10 in plain AAD
ax = r                           # AH cleared
sf = r >> 7 & 1
zf = r == 0
pf = parity(r)
of = af = cf = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AAD imm8` not in 64-bit mode
`imm8`	explicit	read
`AL`	implicit	read, write
`AH`	implicit	read, write
`RFLAGS`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	M	M	U	M	U

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Not in 64-bit mode#