AAM instruction (General-purpose)

AAM divides AL by a base, 10 unless its immediate byte says otherwise, and puts the quotient in AH and the remainder in AL. After a MUL of two unpacked BCD digits, whose product is at most 81, that splits the product into its two decimal digits: 7 times 9 leaves 3Fh, and AAM gives AX = 0603h. It reads only AL, so it splits any byte below 100 into two digits, and a larger one into a quotient of up to 25 and a digit. SF, ZF and PF follow the new AL; OF, AF and CF are undefined, so nothing reports a quotient too large for one digit.

Any base

The base is the second byte of the instruction, D4 0A for plain AAM. Intel’s and AMD’s manuals give octal and base 12 as examples and say that other bases are coded by hand; GNU as 2.44 and Clang 23 also take it as an operand, aam $16 in AT&T syntax, which splits AL into its two hexadecimal digits. A base of 0 raises #DE, as a DIV by zero does. AAD is the inverse, joining two digits before a division, and AAA the adjustment after an addition.

Not in 64-bit mode

Opcode D4 raises #UD in 64-bit mode, so the fixture has no case for AAM: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse aam in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. In our builds with -m32, a function returning x / 10 in AH and x % 10 in AL compiles at -Os in GCC 14 to a DIV of AX by DL and an XCHG of AL and AH, and in Clang 23 to multiplications by constants, neither using AAM. AMD’s Zen 5 guide lists AAM as microcoded, without a latency.

Forms

Every encoding of AAM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AAM imm8` not in 64-bit mode AAM_IMMb	`D4 ib`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

b = base.read()                  # 10 in plain AAM
if b == 0:
    fault(DE)
a = al
r = a % b
ah = a // b
al = r
sf = r >> 7 & 1
zf = r == 0
pf = parity(r)
of = af = cf = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AAM imm8` not in 64-bit mode
`imm8`	explicit	read
`AL`	implicit	read, write
`AH`	implicit	write
`RFLAGS`	implicit	write

Flags

M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	M	M	U	M	U

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Any base#

Not in 64-bit mode#