AAS instruction (General-purpose)

AAS is AAA for subtraction: after a SUB of one unpacked BCD digit from another, it corrects AL and borrows from AH. When the low four bits of AL are above 9, or AF says that the subtraction borrowed from them, it subtracts 6 from AL and 1 from AH, which Intel’s pseudocode writes as 106h taken from AX, and sets AF and CF; otherwise it clears both. The high four bits of AL are cleared either way, and OF, SF, ZF and PF are undefined. With ASCII digits, ‘3’ minus ‘5’ (33h minus 35h) leaves FEh with AF set, and AAS with AH = 0 gives AX = FF08h and CF set: 8 in AL and a borrow of 1 in AH, which is -10 + 8 = -2.

Which AL is corrected

AMD’s Volume 3 tests whether AL as a whole is above 9, where Intel’s manual, the Operation section and AMD’s own text for AAA test the low four bits. The two differ for an AL above 9 whose low digit is 9 or less with AF clear, such as 30h, left by a SUB of an unpacked digit from an ASCII one: by Intel’s rule AAS leaves AH alone and clears CF. The difference of two digits of the same kind, both ASCII or both unpacked, is 00h to 09h or has AF set, and there the two rules agree.

Not in 64-bit mode

Opcode 3F raises #UD in 64-bit mode, so the fixture has no case for AAS: the probe runs there and lists the form as not run. GNU as 2.44 and Clang 23 refuse aas in 64-bit code, and GCC 14 and Clang 23 have no intrinsic for it. AMD’s Zen 5 guide lists AAS as microcoded, without a latency.

Forms

Every encoding of AAS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AAS` not in 64-bit mode AAS	`3F`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = ax
if (a & 0xF) > 9 or af:          # the low digit borrowed
    a -= 0x106                   # AL - 6, its borrow from AH, and AH - 1
    af = cf = 1
else:
    af = cf = 0
ax = a & 0xFF0F                  # AL keeps its low four bits
of = sf = zf = pf = UNDEFINED

Not run on a processor: the instruction does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AAS` not in 64-bit mode
`AL`	implicit	read, write
`AH`	implicit	read, write
`RFLAGS`	implicit	read, write

Flags

T tested, M modified, U undefined; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
U	U	U	TM	U	M

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Which AL is corrected#

Not in 64-bit mode#