ADC

ADC adds its source and CF to its destination, and leaves the carry out of that sum in CF. That makes it the link of a chain: to add numbers wider than a register, ADD the lowest words and ADC each higher pair, every ADC taking the carry of the one before.

Wide additions in C#

GCC 14 and Clang 23 at -O2 compile an unsigned __int128 addition to add on the low halves and adc on the high halves, the result in RDX:RAX. For longer numbers both offer carry built-ins: __builtin_addcll(a, b, carry_in, &carry_out), called once per word with the carry passed along, becomes one ADD and a row of ADCs, with the loads and stores between them done by MOV, which leaves CF alone.

A loop over the words is harder, because the loop’s own CMP overwrites CF. With the _addcarry_u64 intrinsic in a loop, both compilers save the carry in a register with SETC (or SETB) after each ADC and recreate it at the top with add al, -1, which sets CF exactly when AL is not 0; Clang also unrolls by four and keeps CF in the flags within each pass. Hand-written code can keep CF across the whole loop by stepping with LEA and counting with DEC, neither of which writes CF, as in Example 3-26 of Intel’s Optimization Reference Manual.

Adding a condition#

ADC with 0 adds the carry alone, and CMP puts an unsigned comparison into CF, so a + (b < c) on unsigned numbers becomes cmp rsi, rdx and adc rax, 0, without a SETcc.

Related instructions#

SBB is the subtracting counterpart. ADCX and ADOX add with a carry in CF or OF only, so that two chains can run side by side; Intel’s manual presents them, with MULX, as a way to speed up arithmetic on large integers (Section 2.8.5.10). APX gives ADC a form with a new destination register but, unlike ADD, none that leaves the flags unchanged.

Intel’s manual notes that ADC and SBB became faster in Sandy Bridge, with a throughput of one per cycle instead of 1.5 to 2 cycles before (Section 3.5.1.3).

In the optimization guide

What the optimization guide says about ADC, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• What Broadwell changed: A micro-op of Haswell’s reads three inputs only for FMA, so ADC, SBB and CMOV, which read two registers and the flags, are two micro-ops each; Broadwell makes them one, though stores and blends stay at two.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # with LOCK: one atomic read-modify-write
b = sext(src)                    # an immediate is sign-extended to OSIZE
c = cf                           # the carry in
flags = add_flags(a, b, c)
dest.write(a + b + c)            # a 32-bit register: bits 63:32 cleared

a = src1.read()
b = sext(src2)                   # an immediate is sign-extended to OSIZE
c = cf                           # the carry in
flags = add_flags(a, b, c)
dest.write(a + b + c)            # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

ADC m8, imm8 ADC m8, r8 ADC m16/32/64, imm16/32 ADC m16/32/64, imm8 ADC m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions

More APX instructions

• AADD
• AAND
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions