x86-64.net

Instruction

ADC

Adds two integers and the carry flag, the step that chains multi-word additions; APX adds a three-operand form.

Extensions
Forms
48 (24 Legacy, 24 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of ADC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ADC m8, imm8 ADC_MEMb_IMMb_80r280 /2 ibBase instruction set
ADC r8, imm8 ADC_GPR8_IMMb_80r280 /2 ibBase instruction set
ADC m16/32/64, imm16/32 ADC_MEMv_IMMz81 /2 iw/idBase instruction set
ADC r16/32/64, imm16/32 ADC_GPRv_IMMz81 /2 iw/idBase instruction set
ADC m8, imm8 not in 64-bit mode ADC_MEMb_IMMb_82r282 /2 ibBase instruction set
ADC r8, imm8 not in 64-bit mode ADC_GPR8_IMMb_82r282 /2 ibBase instruction set
ADC m16/32/64, imm8 ADC_MEMv_IMMb83 /2 ibBase instruction set
ADC r16/32/64, imm8 ADC_GPRv_IMMb83 /2 ibBase instruction set
ADC m8, r8 ADC_MEMb_GPR810 /rBase instruction set
ADC r8, r8 ADC_GPR8_GPR8_1010 /rBase instruction set
ADC m16/32/64, r16/32/64 ADC_MEMv_GPRv11 /rBase instruction set
ADC r16/32/64, r16/32/64 ADC_GPRv_GPRv_1111 /rBase instruction set
ADC r8, m8 ADC_GPR8_MEMb12 /rBase instruction set
ADC r8, r8 ADC_GPR8_GPR8_1212 /rBase instruction set
ADC r16/32/64, m16/32/64 ADC_GPRv_MEMv13 /rBase instruction set
ADC r16/32/64, r16/32/64 ADC_GPRv_GPRv_1313 /rBase instruction set
ADC AL, imm8 ADC_AL_IMMb14 ibBase instruction set
ADC rAX, imm16/32 ADC_OrAX_IMMz15 iw/idBase instruction set
LOCK ADC m8, imm8 ADC_LOCK_MEMb_IMMb_80r280 /2 ibBase instruction set
LOCK ADC m16/32/64, imm16/32 ADC_LOCK_MEMv_IMMz81 /2 iw/idBase instruction set
LOCK ADC m8, imm8 not in 64-bit mode ADC_LOCK_MEMb_IMMb_82r282 /2 ibBase instruction set
LOCK ADC m16/32/64, imm8 ADC_LOCK_MEMv_IMMb83 /2 ibBase instruction set
LOCK ADC m8, r8 ADC_LOCK_MEMb_GPR810 /rBase instruction set
LOCK ADC m16/32/64, r16/32/64 ADC_LOCK_MEMv_GPRv11 /rBase instruction set
ADC r8, r8 ADC_GPR8i8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 10 /r
EVEX.LLZ.NP.MAP4.WIG 12 /r		APX_F
ADC m8, r8 ADC_MEMi8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 10 /rAPX_F
ADC r16/32/64, r16/32/64, imm8 NDD ADC_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /2 ib ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, m16/32/64, imm8 NDD ADC_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /2 ib ND=1APX_F + APX_NCI_NDD_NF
ADC r8, r8, r8 NDD ADC_GPR8i8_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 10 /r ND=1
EVEX.LLZ.NP.MAP4.WIG 12 /r ND=1		APX_F + APX_NCI_NDD_NF
ADC r8, m8, r8 NDD ADC_GPR8i8_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 10 /r ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, r16/32/64 ADC_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 11 /r
EVEX.LLZ.NP.MAP4.SCALABLE 13 /r		APX_F
ADC m16/32/64, r16/32/64 ADC_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 11 /rAPX_F
ADC r16/32/64, r16/32/64, r16/32/64 NDD ADC_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 11 /r ND=1
EVEX.LLZ.NP.MAP4.SCALABLE 13 /r ND=1		APX_F + APX_NCI_NDD_NF
ADC r16/32/64, m16/32/64, r16/32/64 NDD ADC_GPRv_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 11 /r ND=1APX_F + APX_NCI_NDD_NF
ADC r8, m8 ADC_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG 12 /rAPX_F
ADC r8, r8, m8 NDD ADC_GPR8i8_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 12 /r ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, m16/32/64 ADC_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 13 /rAPX_F
ADC r8, r8, imm8 NDD ADC_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /2 ib ND=1APX_F + APX_NCI_NDD_NF
ADC r8, m8, imm8 NDD ADC_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /2 ib ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, r16/32/64, m16/32/64 NDD ADC_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 13 /r ND=1APX_F + APX_NCI_NDD_NF
ADC r8, imm8 ADC_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /2 ibAPX_F
ADC m8, imm8 ADC_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /2 ibAPX_F
ADC r16/32/64, imm16/32 ADC_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /2 iw/idAPX_F
ADC m16/32/64, imm16/32 ADC_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /2 iw/idAPX_F
ADC r16/32/64, r16/32/64, imm16/32 NDD ADC_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /2 iw/id ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, m16/32/64, imm16/32 NDD ADC_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /2 iw/id ND=1APX_F + APX_NCI_NDD_NF
ADC r16/32/64, imm8 ADC_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /2 ibAPX_F
ADC m16/32/64, imm8 ADC_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /2 ibAPX_F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.