ADCX

ADCX adds its source and CF to its destination and puts the carry out in CF, as ADC does, but it changes no other flag. Its twin ADOX does the same with OF as the carry, so two carry chains can run through the same stretch of code without disturbing each other.

Two chains in one row#

In a multiplication of numbers of several words, each 128-bit product of two words has a low half for one column and a high half for the next. MULX writes no flags, so one row of the multiplication can add the low halves in a CF chain and the high halves in an OF chain, interleaved. With the multiplier in RDX, the other factor at RSI and the row’s sums in R10 upward:

1. xor eax, eax clears CF and OF at once and leaves a zero in RAX.
2. mulx r9, r8, [rsi] puts the first product’s high half in R9 and its low half in R8.
3. adcx r10, r8 adds the low half to word 0, carrying in CF; adox r11, r9 adds the high half to word 1, carrying in OF.
4. mulx r9, r8, [rsi+8], adcx r11, r8 and adox r12, r9 do the next word, each chain taking the carry it left, and so on.
5. An ADCX and an ADOX of RAX into the words above the row absorb the last two carries, as there is no immediate form.

Intel’s optimization manual presents ADCX and ADOX, with MULX, as a way to speed up arithmetic on large integers (Section 2.8.5.10).

Not from C#

The intrinsic _addcarryx_u64(c, a, b, &sum) (-madx) has the signature of _addcarry_u64, and GCC 14 and Clang 23 at -O2 compile both to ADC, even with -march=znver5: ADCX appears only in hand-written assembly.

Forms and speed#

A 32-bit destination takes the carry out of bit 31 and has bits 63:32 cleared, as Zen 5’s cases show. APX adds EVEX forms reaching its new registers and an NDD form with a separate destination.

AMD’s Zen 5 instruction table lists ADCX like ADC: one macro-op, a latency of one cycle, one per cycle. Intel’s manual places it with ADC on the shift units of Golden Cove (Table 2-4). ADX is in no x86-64 level.

In the optimization guide

What the optimization guide says about ADCX, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Integer execution: The E-cores keep the arithmetic flags as one register, so ADCX and ADOX depend on each other unless an instruction that writes all flags comes between them.

Haswell and Broadwell

• What Broadwell changed: Broadwell adds ADCX and ADOX, RDSEED and PREFETCHW, which -march=broadwell enables in LLVM; code built that way can fault on Haswell, which has none of them.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
b = src.read()
c = cf                           # the carry in
r = a + b + c
cf = r >> OSIZE & 1              # the carry out; OF, SF, ZF, AF and PF
                                 # keep their values
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

a = src1.read()
b = src2.read()
c = cf                           # the carry in
r = a + b + c
cf = r >> OSIZE & 1              # the carry out; no other flag changes
dest.write(r)                    # the new destination: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More ADX instructions

• ADOX

More APX instructions

• AADD
• AAND
• ADC
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions