ADD

ADD shows every kind of form that APX gives an integer instruction, so its table is a good map of the whole extension.

• Legacy forms (opcodes 00 to 05 and 80 to 83) work as they always have. A REX2 prefix in front of them reaches R16 to R31; XED does not list REX2 forms separately, because the prefix changes only register numbers.
• LOCK forms are the memory-destination forms with a LOCK prefix, which make the read-modify-write atomic. APX promotes no LOCK-prefixed instruction, so atomic additions keep the legacy encoding, with REX2 when the address uses an extended register.
• EVEX forms without ND (map 4) do the same two-operand addition. With NF=1 they leave the flags untouched.
• EVEX forms with ND=1 take a separate destination register, so ADD r10, r11, r12 writes r11 + r12 to r10 and keeps both sources. One of the sources may be memory; the destination never is. The result is zero-extended to 64 bits even for 8- and 16-bit operands, and NF may be 0 or 1.

XED places the plain EVEX forms in the APX_F ISA set and the forms that use ND or NF in APX_F_N3, which also requires CPUID leaf 29H (APX_NCI_NDD_NF).

In the optimization guide

What the optimization guide says about ADD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Move elimination: Golden Cove goes further: Agner Fog found that adding a small constant to a register sometimes takes no time, and LLVM’s model gives add and sub of an 8-bit immediate to a 64-bit register no micro-op at all (Golden Cove).

Golden Cove and Raptor Cove

• Integer execution: Register-to-register moves and zeroing idioms are handled when micro-ops are renamed, and adding a small constant to a register sometimes takes no cycle either.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()                  # with LOCK: one atomic read-modify-write
b = sext(src)                    # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 (APX) leaves the flags as they were
    flags = add_flags(a, b)
dest.write(a + b)                # a 32-bit register: bits 63:32 cleared

a = src1.read()
b = sext(src2)                   # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 leaves the flags as they were
    flags = add_flags(a, b)
dest.write(a + b)                # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

ADD m8, imm8 ADD m8, r8 ADD m16/32/64, imm16/32 ADD m16/32/64, imm8 ADD m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

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More APX instructions

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All 88 APX instructions