x86-64.net

Instruction

ADD

Adds two integers and sets the arithmetic flags; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
60 (24 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

ADD shows every kind of form that APX gives an integer instruction, so its table is a good map of the whole extension.

  • Legacy forms (opcodes 00 to 05 and 80 to 83) work as they always have. A REX2 prefix in front of them reaches R16 to R31; XED does not list REX2 forms separately, because the prefix changes only register numbers.
  • LOCK forms are the memory-destination forms with a LOCK prefix, which make the read-modify-write atomic. APX promotes no LOCK-prefixed instruction, so atomic additions keep the legacy encoding, with REX2 when the address uses an extended register.
  • EVEX forms without ND (map 4) do the same two-operand addition. With NF=1 they leave the flags untouched.
  • EVEX forms with ND=1 take a separate destination register, so ADD r10, r11, r12 writes r11 + r12 to r10 and keeps both sources. One of the sources may be memory; the destination never is. The result is zero-extended to 64 bits even for 8- and 16-bit operands, and NF may be 0 or 1.

XED places the plain EVEX forms in the APX_F ISA set and the forms that use ND or NF in APX_F_N3, which also requires CPUID leaf 29H (APX_NCI_NDD_NF).

Forms

Every encoding of ADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ADD m8, imm8 ADD_MEMb_IMMb_80r080 /0 ibBase instruction set
ADD r8, imm8 ADD_GPR8_IMMb_80r080 /0 ibBase instruction set
ADD m16/32/64, imm16/32 ADD_MEMv_IMMz81 /0 iw/idBase instruction set
ADD r16/32/64, imm16/32 ADD_GPRv_IMMz81 /0 iw/idBase instruction set
ADD m8, imm8 not in 64-bit mode ADD_MEMb_IMMb_82r082 /0 ibBase instruction set
ADD r8, imm8 not in 64-bit mode ADD_GPR8_IMMb_82r082 /0 ibBase instruction set
ADD m16/32/64, imm8 ADD_MEMv_IMMb83 /0 ibBase instruction set
ADD r16/32/64, imm8 ADD_GPRv_IMMb83 /0 ibBase instruction set
ADD m8, r8 ADD_MEMb_GPR800 /rBase instruction set
ADD r8, r8 ADD_GPR8_GPR8_0000 /rBase instruction set
ADD m16/32/64, r16/32/64 ADD_MEMv_GPRv01 /rBase instruction set
ADD r16/32/64, r16/32/64 ADD_GPRv_GPRv_0101 /rBase instruction set
ADD r8, m8 ADD_GPR8_MEMb02 /rBase instruction set
ADD r8, r8 ADD_GPR8_GPR8_0202 /rBase instruction set
ADD r16/32/64, m16/32/64 ADD_GPRv_MEMv03 /rBase instruction set
ADD r16/32/64, r16/32/64 ADD_GPRv_GPRv_0303 /rBase instruction set
ADD AL, imm8 ADD_AL_IMMb04 ibBase instruction set
ADD rAX, imm16/32 ADD_OrAX_IMMz05 iw/idBase instruction set
LOCK ADD m8, imm8 ADD_LOCK_MEMb_IMMb_80r080 /0 ibBase instruction set
LOCK ADD m16/32/64, imm16/32 ADD_LOCK_MEMv_IMMz81 /0 iw/idBase instruction set
LOCK ADD m8, imm8 not in 64-bit mode ADD_LOCK_MEMb_IMMb_82r082 /0 ibBase instruction set
LOCK ADD m16/32/64, imm8 ADD_LOCK_MEMv_IMMb83 /0 ibBase instruction set
LOCK ADD m8, r8 ADD_LOCK_MEMb_GPR800 /rBase instruction set
LOCK ADD m16/32/64, r16/32/64 ADD_LOCK_MEMv_GPRv01 /rBase instruction set
ADD r8, r8 ADD_GPR8i8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 00 /r
EVEX.LLZ.NP.MAP4.WIG 02 /r		APX_F
ADD m8, r8 ADD_MEMi8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 00 /rAPX_F
ADD r8, r8 NF ADD_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 00 /r NF=1
EVEX.LLZ.NP.MAP4.WIG 02 /r NF=1		APX_F + APX_NCI_NDD_NF
ADD m8, r8 NF ADD_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 00 /r NF=1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, r16/32/64, imm8 NDD NF optional ADD_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, m16/32/64, imm8 NDD NF optional ADD_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r8, r8, r8 NDD NF optional ADD_GPR8i8_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 00 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG 02 /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
ADD r8, m8, r8 NDD NF optional ADD_GPR8i8_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 00 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, r16/32/64 ADD_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 01 /r
EVEX.LLZ.NP.MAP4.SCALABLE 03 /r		APX_F
ADD m16/32/64, r16/32/64 ADD_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 01 /rAPX_F
ADD r16/32/64, r16/32/64 NF ADD_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 01 /r NF=1
EVEX.LLZ.NP.MAP4.SCALABLE 03 /r NF=1		APX_F + APX_NCI_NDD_NF
ADD m16/32/64, r16/32/64 NF ADD_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 01 /r NF=1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, r16/32/64, r16/32/64 NDD NF optional ADD_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 01 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE 03 /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
ADD r16/32/64, m16/32/64, r16/32/64 NDD NF optional ADD_GPRv_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 01 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r8, m8 ADD_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG 02 /rAPX_F
ADD r8, m8 NF ADD_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 02 /r NF=1APX_F + APX_NCI_NDD_NF
ADD r8, r8, m8 NDD NF optional ADD_GPR8i8_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 02 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, m16/32/64 ADD_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 03 /rAPX_F
ADD r16/32/64, m16/32/64 NF ADD_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 03 /r NF=1APX_F + APX_NCI_NDD_NF
ADD r8, r8, imm8 NDD NF optional ADD_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r8, m8, imm8 NDD NF optional ADD_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /0 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, r16/32/64, m16/32/64 NDD NF optional ADD_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 03 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r8, imm8 ADD_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /0 ibAPX_F
ADD m8, imm8 ADD_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /0 ibAPX_F
ADD r8, imm8 NF ADD_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ADD m8, imm8 NF ADD_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, imm16/32 ADD_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/idAPX_F
ADD m16/32/64, imm16/32 ADD_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/idAPX_F
ADD r16/32/64, imm16/32 NF ADD_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/id NF=1APX_F + APX_NCI_NDD_NF
ADD m16/32/64, imm16/32 NF ADD_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/id NF=1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, r16/32/64, imm16/32 NDD NF optional ADD_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, m16/32/64, imm16/32 NDD NF optional ADD_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /0 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
ADD r16/32/64, imm8 ADD_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ibAPX_F
ADD m16/32/64, imm8 ADD_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ibAPX_F
ADD r16/32/64, imm8 NF ADD_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ib NF=1APX_F + APX_NCI_NDD_NF
ADD m16/32/64, imm8 NF ADD_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /0 ib NF=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.