ADDPD instruction (SSE2)

ADDPD adds the two doubles of its second operand to those of its first, rounding each sum as MXCSR says. VADDPD is the same operation in VEX and EVEX encodings; its page and ADDPS’s cover the tie rule, the invalid sums and flushing to zero. What this SSE2 form has of its own:

Two operands. The sum replaces the first operand, so code that still needs that value copies it first.
The bits above 127 stay. The legacy form leaves the rest of the YMM or ZMM register as it was, where VADDPD on an xmm register clears it; code that mixes the two kinds pays for the switch, as SSE and AVX explains.
Aligned memory. A memory operand must sit on a 16-byte boundary, or the instruction raises #GP.

Zen 5’s recorded cases follow the rounding rules to the last bit. Under MXCSR’s default, 1F80H, addpd xmm12, xmm6 turned 1 + 2^-53, halfway between two doubles, into 1, and 1 + 1.5 times 2^-53 into 1 + 2^-52, setting PE. With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), the memory form doubled 10^300 and 10^-300 exactly and set no flag.

Pairs of doubles in compiled code

SSE2 belongs to every x86-64 processor, so compilers use this instruction with no option, and not only in loops. In our builds at -O2 for the default target, GCC 14 and Clang 23 compile r->x = a->x + b->x; r->y = a->y + b->y; on a struct of two doubles to two MOVUPD loads and one addition of the pair, and *r = *a + *b on pointers to double _Complex the same way. Passed by value, each complex argument arrives in two registers, and the sum becomes two ADDSD. Over global arrays of fixed size, a[i] = b[i] + c[i] takes c straight from memory, as addpd xmm0, XMMWORD PTR c[rax] in GCC; a running sum over such an array stays scalar without -ffast-math, for the reason the ADDPS page gives.

AMD’s latency spreadsheet for Zen 5 lists ADDPD with VADDPD’s figures: one macro-op on pipes FP2 and FP3, a latency of 2 cycles and two per cycle.

In the optimization guide

What the optimization guide says about ADDPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: Packed adds and multiplies are slower than scalar on Silvermont, mulpd most of all; Goldmont runs them one a cycle.

Forms

Every encoding of ADDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ADDPD xmm, m128` ADDPD_XMMpd_MEMpd	`66 0F 58 /r`	SSE2
`ADDPD xmm, xmm` ADDPD_XMMpd_XMMpd	`66 0F 58 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each double of the result comes from the double in the same place in each source.

Result double i comes from double i of xmm1 and xmm2. Result doubles 1 to 0: a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    xmm1.f64[i] = add(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ADDPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_pd` `__m128d _mm_add_pd(__m128d __a, __m128d __b)`	`ADDPD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Pairs of doubles in compiled code#