ADDPS instruction (SSE)

ADDPS adds four pairs of singles at once and rounds each sum as MXCSR’s rounding control says, to nearest even unless a program changes it. Its scalar sibling ADDSS adds only the lowest pair and keeps the other three elements of the destination. Since SSE and SSE2 are part of every x86-64 processor (see the baseline), compilers do ordinary float and double arithmetic with the scalar forms rather than with the x87 unit: GCC 14 and Clang 23 at -O2 compile a + b on two floats to addss xmm0, xmm1.

Vectorized loops

The packed form comes from intrinsics such as _mm_add_ps and from vectorized loops. Clang 23 at -O2 turns a[i] = b[i] + c[i] over floats into ADDPS for any count, with a scalar loop for the elements left over; GCC 14 at -O2 did so when the count was the constant 1024, but kept the scalar loop for a count passed as an argument.

A sum of the elements is another matter. Floating-point addition is not associative: adding in four interleaved partial sums rounds differently from adding in order, so neither compiler vectorizes s += a[i] at -O2. With -ffast-math, which allows the reordering, Clang 23 does it with ADDPS.

Legacy, VEX and EVEX

The legacy form overwrites its first source, keeps bits 128 and up of the register, and needs a memory operand aligned to 16 bytes, or it raises #GP. Compilers fold an aligned load into it and load other data with MOVUPS first.
VADDPS (VEX) writes a third register, adds 256-bit vectors too, accepts memory at any alignment and clears the bits above its result.
The EVEX forms add masking, one single from memory repeated to every element ({1to16}) and, between 512-bit registers, a rounding mode in the instruction ({er}) that overrides MXCSR’s and records no exceptions.

Special values

The cases recorded on Zen 5 show the tie rule: 1 + 2^-24 lies halfway between 1 and the next single and gives 1, while 1 + 1.5 * 2^-24 rounds up to it. An infinity plus an infinity of the other sign is an invalid operation. With the exception masked, as MXCSR’s initial value 1F80H masks them all, the result is the QNaN floating-point indefinite, FFC00000H, and MXCSR’s IE flag is set; unmasked, the instruction raises #XM and writes no element. MULPS has more on MXCSR.

In the optimization guide

What the optimization guide says about ADDPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Vectors and cryptography: Packed adds and multiplies are slower than scalar on Silvermont, mulpd most of all; Goldmont runs them one a cycle.

Forms

Every encoding of ADDPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ADDPS xmm, m128` ADDPS_XMMps_MEMps	`NP 0F 58 /r`	SSE
`ADDPS xmm, xmm` ADDPS_XMMps_XMMps	`NP 0F 58 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm1 and xmm2. Result singles 3 to 0: a3+b3, a2+b2, a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    xmm1.f32[i] = add(a, b)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ADDPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_ps` `__m128 _mm_add_ps(__m128 __a, __m128 __b)`	`ADDPS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Vectorized loops#

Legacy, VEX and EVEX#

Special values#