ADDSD instruction (SSE2)

ADDSD adds the low double of its source to the low double of its destination and keeps the high double. It is SSE2’s scalar form of ADDPD; ADDSS covers what the scalar forms share, from the kept elements to the memory operand at any alignment, and VADDSD is the VEX and EVEX form. GCC 14 and Clang 23 at -O2 compile a + b over double to addsd xmm0, xmm1, and the sum of a float and a double, returned as a float, to CVTSS2SD, ADDSD and CVTSD2SS. Zen 5’s two recorded cases:

With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), 1 + 2^-52, the double after 1, plus 1 from memory gave 2 and set PE: the exact sum lies halfway between 2 and the next double, and rounding toward zero drops it.
Under MXCSR’s default, -0 plus +0 gave +0, while the high doubles held a signaling NaN in the source and a quiet one in the destination; IE stayed clear, as only the low element takes part.

Compensated sums

The order of floating-point additions changes the result, and at -O2 the compilers keep it: in our builds, s += da[i] over a global array of doubles is a chain of ADDSD reading memory, unrolled by two in GCC and by four in Clang. Kahan’s compensated summation relies on that order:

double y = da[i] - c;
double t = s + y;
c = (t - s) - y;
s = t;

Both compilers keep its ADDSD and three SUBSD in the loop. With -ffast-math they may reassociate, the correction term is algebraically zero, and it disappears: each compiler emits the same ADDPD loop for this function as for the plain sum, and the compensation is lost without a warning.

AMD’s latency spreadsheet for Zen 5 lists ADDSD at 2 cycles on pipes FP2 and FP3. The memory form reads eight bytes at any alignment, and the legacy form keeps bits 255:128 (see mixing SSE and AVX).

Forms

Every encoding of ADDSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ADDSD xmm, m64` ADDSD_XMMsd_MEMsd	`F2 0F 58 /r`	SSE2
`ADDSD xmm, xmm` ADDSD_XMMsd_XMMsd	`F2 0F 58 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = add(xmm1.f64[0], src2.f64[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ADDSD xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_sd` `__m128d _mm_add_sd(__m128d __a, __m128d __b)`	`ADDSD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Compensated sums#