ADDSS instruction (SSE)

ADDSS adds the low single of its source to the low single of its destination and keeps singles 1 to 3 of the destination as they were. It is the scalar form of ADDPS, whose page covers the rounding, the tie rule and the invalid sum of two opposite infinities; VADDSS is the VEX and EVEX form. SSE belongs to every x86-64 processor, so this is what C’s float addition compiles to: GCC 14 and Clang 23 at -O2 turn a + b into addss xmm0, xmm1.

Zeros and a sum too large

Among the 36 cases recorded on Zen 5:

-0 plus +0 gave +0 under MXCSR’s default, 1F80H. That is why both compilers keep x + 0.0f as an addition of a zeroed register, while x - 0.0f, which gives x for every input under that rounding, compiles to nothing.
With MXCSR at FF80H (round toward zero, FTZ set), the largest single plus itself gave the largest single again rather than infinity, and set OE and PE.
The smallest denormal plus itself gave 2^-148 exactly. DE was set but UE was not: with underflow masked, only a result both tiny and inexact reports it (Intel’s Volume 1, Section 4.9.1.5).
With IM clear (MXCSR 1F00H), a signaling NaN in the destination raised #XM and left the register as it was.

The other three singles

Compiled C code never reads them, but the processor writes them back, so the instruction depends on whatever last wrote its destination. For ADDSS that costs nothing extra, since the destination’s low single is the first addend anyway; AMD’s guide for Zen 5 lists only instructions whose result does not otherwise read the destination, such as SQRTSS and CVTSI2SS, under its merge optimization (Section 2.11.5). The legacy form also keeps bits 255:128 (see mixing SSE and AVX).

The memory form reads four bytes at any alignment, so the compilers fold scalar loads into it: in our builds, x + fa[5] over a global array is addss xmm0, DWORD PTR fa[rip+20], an address that is not a multiple of 16. A running sum, s += fa[i], stays a chain of such additions, four per iteration, in both compilers, for the reason the ADDPS page gives. AMD’s latency spreadsheet for Zen 5 lists ADDSS at 2 cycles on pipes FP2 and FP3.

Forms

Every encoding of ADDSS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ADDSS xmm, m32` ADDSS_XMMss_MEMss	`F3 0F 58 /r`	SSE
`ADDSS xmm, xmm` ADDSS_XMMss_XMMss	`F3 0F 58 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from single 0 of xmm1 and xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = add(xmm1.f32[0], src2.f32[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 36 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ADDSS xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_add_ss` `__m128 _mm_add_ss(__m128 __a, __m128 __b)`	`ADDSS xmm, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Zeros and a sum too large#

The other three singles#