ADDSUBPD

ADDSUBPD subtracts in the low element and adds in the high one: the first operand becomes a[0] - b[0] and a[1] + b[1]. Each half rounds under MXCSR as SUBPD or ADDPD would, with the same flags. It came with SSE3, so code built for the first x86-64 level cannot use it; ADDSUBPS alternates over four singles, VADDSUBPD over two or four doubles with a separate destination, and FMA’s VFMADDSUB231PD fuses a multiply into the same pattern. As a legacy SSE instruction it keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

On Zen 5, addsubpd xmm12, xmm6 with 2.0 and 0.5 in XMM12 and -1.0 and -0.5 in XMM6 gave 3.0 below and +0.0 above. With a signaling NaN in the low double of XMM1, addsubpd xmm1, xmmword ptr [mem] gave that NaN made quiet, 7FF8000000012345h, and set IE; above, a quiet NaN plus 1.0 gave the NaN.

Complex multiplication#

The pattern fits a product of complex numbers, (a + bi)(c + di) = (ac - bd) + (ad + bc)i: multiply (c, d) by a in both halves, multiply the swapped (d, c) by b, and one ADDSUBPD gives the real part below and the imaginary part above. In our builds at -O2, GCC 14 and Clang 23 keep a loop of r[i] = a[i] * b[i] over double complex scalar, since C’s rules make them check each product for NaNs and call __muldc3. With -fcx-limited-range or -ffast-math and -march=x86-64-v2, both vectorize it that way: GCC duplicates the halves of a[i] with UNPCKLPD and UNPCKHPD and swaps b[i] with PALIGNR, Clang loads the halves with MOVDDUP and swaps with SHUFPD, and both finish with MULPD and ADDSUBPD.

Plain alternating arithmetic, r[i] = a[i] - b[i] and r[i+1] = a[i+1] + b[i+1], becomes one ADDSUBPD per pair with -march=x86-64-v2; for the default target, both compilers compute a SUBPD and an ADDPD and merge their halves with a MOVSD.

AMD’s latency spreadsheet for Zen 5 lists ADDSUBPD like ADDPD: one macro-op on pipes FP2 and FP3, with a latency of 2 cycles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    if i % 2 == 0:
        xmm1.f64[i] = sub(a, b)
    else:
        xmm1.f64[i] = add(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDSUBPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPS
• FISTTP
• HADDPD
• HADDPS
• HSUBPD
• HSUBPS
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP