ADDSUBPS

ADDSUBPS subtracts in the even elements and adds in the odd ones, giving (a0 - b0, a1 + b1, a2 - b2, a3 + b3) over four singles. ADDSUBPD explains the pattern and the complex product it serves, with two doubles; VADDSUBPS is the VEX form, with a separate destination and eight singles in a ymm register. ADDSUBPS came with SSE3, part of x86-64-v2; as a legacy SSE instruction it keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Zen 5’s recorded cases:

• With MXCSR at FFC0H (round toward zero, FTZ and DAZ set), addsubps xmm1, xmmword ptr [mem] gave 1 + 2^-24 as 1 and 1 - 1.5 times 2^-24 as 3F7FFFFEH, both truncated, and 1 + (-2^-24) as 3F7FFFFFH, exactly; PE was set. Below, two quiet NaNs gave the register’s.
• With signaling NaNs among the inputs of addsubps xmm1, xmm2, all four results came out as the quiet NaN 7FC12345H, and IE was set.

Complex singles#

In our builds at -O2 with -march=x86-64-v2 -fcx-limited-range, GCC 14 multiplies arrays of float _Complex two products at a time with MOVSLDUP and MOVSHDUP, which duplicate the real and the imaginary parts of a, two MULPS, a shufps xmm2, xmm2, 177 that swaps the parts of b, and one ADDSUBPS. Clang 23 separates the real and imaginary parts with SHUFPS instead, computes each with MULPS, SUBPS and ADDPS, and interleaves them again with UNPCKLPS and UNPCKHPS. Without the option both keep the loop scalar, with a call to __mulsc3 for products that come out NaN. The alternating r[i] = a[i] - b[i]; r[i+1] = a[i+1] + b[i+1] is one ADDSUBPS per four elements in both at x86-64-v2, and SUBPS, ADDPS and two SHUFPS for the default target.

Intel’s optimization manual rotates (x, y) pairs with MOVSLDUP, MOVSHDUP, MULPS and ADDSUBPS (Example 15-2, Section 15.1.1). AMD’s spreadsheet for Zen 5 lists ADDSUBPS like ADDPS: one macro-op on pipes FP2 and FP3, a latency of 2 cycles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    if i % 2 == 0:
        xmm1.f32[i] = sub(a, b)
    else:
        xmm1.f32[i] = add(a, b)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ADDSUBPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE3 instructions

• ADDSUBPD
• FISTTP
• HADDPD
• HADDPS
• HSUBPD
• HSUBPS
• LDDQU
• MOVDDUP
• MOVSHDUP
• MOVSLDUP