ADOX

ADOX adds its source and OF to its destination and puts the carry out in OF, changing no other flag. It is ADCX with OF in place of CF, and exists so that a second carry chain can run beside an ADCX or ADC chain; the ADCX page shows the two working together in a row of a multiplication, with MULX supplying the products.

OF as a carry#

After ADOX, OF holds an unsigned carry, not a signed overflow. In one of Zen 5’s cases, adox rcx, [mem] with RCX all ones, the memory operand 1 and OF clear gave 0 and set OF; CF, already clear, stayed so. ADD on the same values would set CF and clear OF, as -1 plus 1 does not overflow. A JO or SETO after ADOX therefore tests the carry. A chain is started with OF clear, usually by an XOR that zeroes some register, since XOR clears CF and OF together.

Encoding#

ADCX and ADOX share the bytes 0F 38 F6 and differ only in the mandatory prefix: 66 for ADCX, F3 for ADOX. Without a prefix and with a memory operand the same bytes are WRSSD, the shadow-stack write of CET. As for ADCX, the destination is a register of 32 or 64 bits, the source a register or memory, and no form takes an immediate. APX adds EVEX forms reaching its new registers and an NDD form with a separate destination.

Independence depends on the processor#

The two chains help only where the processor renames OF apart from CF. Intel’s optimization manual says that its Core processors rename CF, OF and the other arithmetic flags as separate registers, while Crestmont, an Atom core, keeps them in one: there ADCX and ADOX depend on each other unless an instruction that writes all the flags without reading them comes between, and hand-tuned code gets less parallelism (Section 4.1.9.8). The same manual places ADCX and ADOX on the shift units of Golden Cove (Table 2-4).

AMD’s Zen 5 instruction table lists ADOX as one macro-op with a latency of one cycle, at four per cycle on ALUs 0 to 3, where it gives ADCX and ADC one per cycle.

GCC 14 and Clang 23 at -O2 compile the intrinsic _addcarryx_u64 to ADC, never ADOX, so the instruction comes from hand-written assembly.

In the optimization guide

What the optimization guide says about ADOX, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Integer execution: The E-cores keep the arithmetic flags as one register, so ADCX and ADOX depend on each other unless an instruction that writes all flags comes between them.

Haswell and Broadwell

• What Broadwell changed: Broadwell adds ADCX and ADOX, RDSEED and PREFETCHW, which -march=broadwell enables in LLVM; code built that way can fault on Haswell, which has none of them.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = dest.read()
b = src.read()
c = of                           # the carry in, from OF
r = a + b + c
of = r >> OSIZE & 1              # the carry out, in OF: an unsigned carry,
                                 # not a signed overflow; CF, SF, ZF, AF and
                                 # PF keep their values
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

a = src1.read()
b = src2.read()
c = of                           # the carry in, from OF
r = a + b + c
of = r >> OSIZE & 1              # the unsigned carry out, in OF; no other
                                 # flag changes
dest.write(r)                    # the new destination: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More ADX instructions

• ADCX

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions