x86-64.net

Instruction

ADOX

Adds two unsigned integers and the overflow flag and changes only OF, so a carry chain can run next to an ADCX chain; APX adds a three-operand form.

Extensions
Forms
12 (4 Legacy, 8 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of ADOX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
ADOX r32, r32 ADOX_GPR32d_GPR32dF3 0F 38 F6 /rADX
ADOX r32, m32 ADOX_GPR32d_MEMdF3 0F 38 F6 /rADX
ADOX r64, r64 64-bit mode only ADOX_GPR64q_GPR64qF3 REX.W 0F 38 F6 /rADX
ADOX r64, m64 64-bit mode only ADOX_GPR64q_MEMqF3 REX.W 0F 38 F6 /rADX
ADOX r32, r32 ADOX_GPR32i32_GPR32i32_APXEVEX.LLZ.F3.MAP4.W0 66 /rAPX_F + ADX
ADOX r32, m32 ADOX_GPR32i32_MEMi32_APXEVEX.LLZ.F3.MAP4.W0 66 /rAPX_F + ADX
ADOX r64, r64 ADOX_GPR64i64_GPR64i64_APXEVEX.LLZ.F3.MAP4.W1 66 /rAPX_F + ADX
ADOX r64, m64 ADOX_GPR64i64_MEMi64_APXEVEX.LLZ.F3.MAP4.W1 66 /rAPX_F + ADX
ADOX r32, r32, r32 NDD ADOX_GPR32i32_GPR32i32_GPR32i32_APX_N3EVEX.LLZ.F3.MAP4.W0 66 /r ND=1APX_F + APX_NCI_NDD_NF + ADX
ADOX r32, r32, m32 NDD ADOX_GPR32i32_GPR32i32_MEMi32_APX_N3EVEX.LLZ.F3.MAP4.W0 66 /r ND=1APX_F + APX_NCI_NDD_NF + ADX
ADOX r64, r64, r64 NDD ADOX_GPR64i64_GPR64i64_GPR64i64_APX_N3EVEX.LLZ.F3.MAP4.W1 66 /r ND=1APX_F + APX_NCI_NDD_NF + ADX
ADOX r64, r64, m64 NDD ADOX_GPR64i64_GPR64i64_MEMi64_APX_N3EVEX.LLZ.F3.MAP4.W1 66 /r ND=1APX_F + APX_NCI_NDD_NF + ADX

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
ADOX_ADCX

ADX
CPUID.(EAX=07H,ECX=0):EBX[19] ADX

Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
APX_F_ADX

APX_F + ADX
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[19] ADX

Nova Lake, Diamond Rapids
APX_F_ADX_N3

APX_F + APX_NCI_NDD_NF + ADX
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=0):EBX[19] ADX

Nova Lake, Diamond Rapids

More ADX instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.