Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of AESDEC256KL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
AESDEC256KL xmm, m512 AESDEC256KL_XMMu8_MEMu8F3 0F 38 DF /rKL + KLENABLED

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, m512
Alder Lake100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 19 & 1:            # CR4.KL; clear without Key Locker
    fault(UD)
if not cpuid_leaf(0x19, 0)[1] & 1:
    fault(UD)                    # AESKLE: the AES instructions of
                                 # Key Locker not enabled
if cr0 >> 2 & 1 or not cr4 >> 9 & 1:
    fault(UD)                    # CR0.EM set, CR4.OSFXSR clear
if cr0 >> 3 & 1:
    fault(NM)                    # CR0.TS
h = handle.read()                # 512 bits, not read atomically
meta = low(h, 128)               # the handle's metadata
kind = meta >> 24 & 0xF          # the key type
ok = 1
if meta & ~0x0F000007:
    ok = 0                       # a reserved bit set
if kind != 1:
    ok = 0                       # not an AES-256 key
if meta & 1 and CPL > 0:
    ok = 0                       # for CPL 0 only
if meta >> 2 & 1:
    ok = 0                       # not for decrypting
if ok:
    k = unwrap_key(h)            # the key, or -1 where IWKey's
    ok = k >= 0                  # integrity test rejects h
if ok:
    s = aes_decrypt(xmm1.read(), k, 256)
    xmm1.write(s)                # bits 128 and up as they were
zf = 1 - ok                      # failed: xmm1 as it was
of = sf = af = pf = cf = 0

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no Key Locker, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
AESDEC256KL xmm, m512
xmmexplicitread, write
m512explicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M000

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
KEYLOCKER

KL + KLENABLED
CPUID.(EAX=07H,ECX=0):ECX[23] KL
CPUID.(EAX=19H,ECX=0):EBX[0] KLENABLED

Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sierra Forest, Clearwater Forest

More Key Locker instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-37 (AESDEC256KL)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.