AESENCWIDE256KL instruction (Key Locker)

Forms

Every encoding of AESENCWIDE256KL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AESENCWIDE256KL m512` AESENCWIDE256KL_MEMu8	`F3 0F 38 D8 /2`	KL + KLENABLED + KLWIDE

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`m512`
Alder Lake	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 19 & 1:            # CR4.KL; clear without Key Locker
    fault(UD)
if not cpuid_leaf(0x19, 0)[1] & 1:
    fault(UD)                    # AESKLE: the AES instructions of
                                 # Key Locker not enabled
if not cpuid_leaf(0x19, 0)[1] >> 2 & 1:
    fault(UD)                    # AES_WIDE: no wide instructions
if cr0 >> 2 & 1 or not cr4 >> 9 & 1:
    fault(UD)                    # CR0.EM set, CR4.OSFXSR clear
if cr0 >> 3 & 1:
    fault(NM)                    # CR0.TS
h = handle.read()                # 512 bits, not read atomically
meta = low(h, 128)               # the handle's metadata
kind = meta >> 24 & 0xF          # the key type
ok = 1
if meta & ~0x0F000007:
    ok = 0                       # a reserved bit set
if kind != 1:
    ok = 0                       # not an AES-256 key
if meta & 1 and CPL > 0:
    ok = 0                       # for CPL 0 only
if meta >> 1 & 1:
    ok = 0                       # not for encrypting
if ok:
    k = unwrap_key(h)            # the key, or -1 where IWKey's
    ok = k >= 0                  # integrity test rejects h
if ok:
    for i in range(8):           # XMM0 to XMM7, bits 128 and up
        s = xmm[i]               # as they were
        xmm[i] = aes_encrypt(s, k, 256)
zf = 1 - ok                      # failed: XMM0 to XMM7 as they were
of = sf = af = pf = cf = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no wide Key Locker, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AESENCWIDE256KL m512`
`m512`	explicit	read
`XMM0`	implicit	read, write
`XMM1`	implicit	read, write
`XMM2`	implicit	read, write
`XMM3`	implicit	read, write
`XMM4`	implicit	read, write
`XMM5`	implicit	read, write
`XMM6`	implicit	read, write
`XMM7`	implicit	read, write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	0

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`KEYLOCKER_WIDE` Key Locker	KL + KLENABLED + KLWIDE `CPUID.(EAX=07H,ECX=0):ECX[23]` KL `CPUID.(EAX=19H,ECX=0):EBX[0]` KLENABLED `CPUID.(EAX=19H,ECX=0):EBX[2]` KLWIDE	Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Sierra Forest, Clearwater Forest

AESENCWIDE256KL