x86-64.net

Instruction

AND

Computes the bitwise AND of two operands; APX adds three-operand forms and forms that leave the flags unchanged.

Extensions
Forms
60 (24 Legacy, 36 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of AND that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
AND m8, imm8 AND_MEMb_IMMb_80r480 /4 ibBase instruction set
AND r8, imm8 AND_GPR8_IMMb_80r480 /4 ibBase instruction set
AND m16/32/64, imm16/32 AND_MEMv_IMMz81 /4 iw/idBase instruction set
AND r16/32/64, imm16/32 AND_GPRv_IMMz81 /4 iw/idBase instruction set
AND m8, imm8 not in 64-bit mode AND_MEMb_IMMb_82r482 /4 ibBase instruction set
AND r8, imm8 not in 64-bit mode AND_GPR8_IMMb_82r482 /4 ibBase instruction set
AND m16/32/64, imm8 AND_MEMv_IMMb83 /4 ibBase instruction set
AND r16/32/64, imm8 AND_GPRv_IMMb83 /4 ibBase instruction set
AND m8, r8 AND_MEMb_GPR820 /rBase instruction set
AND r8, r8 AND_GPR8_GPR8_2020 /rBase instruction set
AND m16/32/64, r16/32/64 AND_MEMv_GPRv21 /rBase instruction set
AND r16/32/64, r16/32/64 AND_GPRv_GPRv_2121 /rBase instruction set
AND r8, r8 AND_GPR8_GPR8_2222 /rBase instruction set
AND r8, m8 AND_GPR8_MEMb22 /rBase instruction set
AND r16/32/64, r16/32/64 AND_GPRv_GPRv_2323 /rBase instruction set
AND r16/32/64, m16/32/64 AND_GPRv_MEMv23 /rBase instruction set
AND AL, imm8 AND_AL_IMMb24 ibBase instruction set
AND rAX, imm16/32 AND_OrAX_IMMz25 iw/idBase instruction set
LOCK AND m8, imm8 AND_LOCK_MEMb_IMMb_80r480 /4 ibBase instruction set
LOCK AND m16/32/64, imm16/32 AND_LOCK_MEMv_IMMz81 /4 iw/idBase instruction set
LOCK AND m8, imm8 not in 64-bit mode AND_LOCK_MEMb_IMMb_82r482 /4 ibBase instruction set
LOCK AND m16/32/64, imm8 AND_LOCK_MEMv_IMMb83 /4 ibBase instruction set
LOCK AND m8, r8 AND_LOCK_MEMb_GPR820 /rBase instruction set
LOCK AND m16/32/64, r16/32/64 AND_LOCK_MEMv_GPRv21 /rBase instruction set
AND r8, r8 AND_GPR8i8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 20 /r
EVEX.LLZ.NP.MAP4.WIG 22 /r		APX_F
AND m8, r8 AND_MEMi8_GPR8i8_APXEVEX.LLZ.NP.MAP4.WIG 20 /rAPX_F
AND r8, r8 NF AND_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 20 /r NF=1
EVEX.LLZ.NP.MAP4.WIG 22 /r NF=1		APX_F + APX_NCI_NDD_NF
AND m8, r8 NF AND_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 20 /r NF=1APX_F + APX_NCI_NDD_NF
AND r16/32/64, r16/32/64, imm8 NDD NF optional AND_GPRv_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, m16/32/64, imm8 NDD NF optional AND_GPRv_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r8, r8, r8 NDD NF optional AND_GPR8i8_GPR8i8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 20 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.WIG 22 /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
AND r8, m8, r8 NDD NF optional AND_GPR8i8_MEMi8_GPR8i8_APX_N3EVEX.LLZ.NP.MAP4.WIG 20 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, r16/32/64 AND_GPRv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 21 /r
EVEX.LLZ.NP.MAP4.SCALABLE 23 /r		APX_F
AND m16/32/64, r16/32/64 AND_MEMv_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE 21 /rAPX_F
AND r16/32/64, r16/32/64 NF AND_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 21 /r NF=1
EVEX.LLZ.NP.MAP4.SCALABLE 23 /r NF=1		APX_F + APX_NCI_NDD_NF
AND m16/32/64, r16/32/64 NF AND_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 21 /r NF=1APX_F + APX_NCI_NDD_NF
AND r16/32/64, r16/32/64, r16/32/64 NDD NF optional AND_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 21 /r ND=1 NF=0/1
EVEX.LLZ.NP.MAP4.SCALABLE 23 /r ND=1 NF=0/1		APX_F + APX_NCI_NDD_NF
AND r16/32/64, m16/32/64, r16/32/64 NDD NF optional AND_GPRv_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 21 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r8, m8 AND_GPR8i8_MEMi8_APXEVEX.LLZ.NP.MAP4.WIG 22 /rAPX_F
AND r8, m8 NF AND_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 22 /r NF=1APX_F + APX_NCI_NDD_NF
AND r8, r8, m8 NDD NF optional AND_GPR8i8_GPR8i8_MEMi8_APX_N3EVEX.LLZ.NP.MAP4.WIG 22 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, m16/32/64 AND_GPRv_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE 23 /rAPX_F
AND r16/32/64, m16/32/64 NF AND_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 23 /r NF=1APX_F + APX_NCI_NDD_NF
AND r8, r8, imm8 NDD NF optional AND_GPR8i8_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /4 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r8, m8, imm8 NDD NF optional AND_GPR8i8_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /4 ib ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, r16/32/64, m16/32/64 NDD NF optional AND_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 23 /r ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r8, imm8 AND_GPR8i8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /4 ibAPX_F
AND m8, imm8 AND_MEMi8_IMM8_APXEVEX.LLZ.NP.MAP4.WIG 80 /4 ibAPX_F
AND r8, imm8 NF AND_GPR8i8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /4 ib NF=1APX_F + APX_NCI_NDD_NF
AND m8, imm8 NF AND_MEMi8_IMM8_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /4 ib NF=1APX_F + APX_NCI_NDD_NF
AND r16/32/64, imm16/32 AND_GPRv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/idAPX_F
AND m16/32/64, imm16/32 AND_MEMv_IMMz_APXEVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/idAPX_F
AND r16/32/64, imm16/32 NF AND_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/id NF=1APX_F + APX_NCI_NDD_NF
AND m16/32/64, imm16/32 NF AND_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/id NF=1APX_F + APX_NCI_NDD_NF
AND r16/32/64, r16/32/64, imm16/32 NDD NF optional AND_GPRv_GPRv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, m16/32/64, imm16/32 NDD NF optional AND_GPRv_MEMv_IMMz_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /4 iw/id ND=1 NF=0/1APX_F + APX_NCI_NDD_NF
AND r16/32/64, imm8 AND_GPRv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ibAPX_F
AND m16/32/64, imm8 AND_MEMv_IMM8_APXEVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ibAPX_F
AND r16/32/64, imm8 NF AND_GPRv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ib NF=1APX_F + APX_NCI_NDD_NF
AND m16/32/64, imm8 NF AND_MEMv_IMM8_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /4 ib NF=1APX_F + APX_NCI_NDD_NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to AND, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_kand_mask32 __mmask32 _kand_mask32(__mmask32 __A, __mmask32 __B)

AND r16/32/64, r16/32/64 Legacy -mavx512bw

_kand_mask64 __mmask64 _kand_mask64(__mmask64 __A, __mmask64 __B)

AND r16/32/64, r16/32/64 Legacy -mavx512bw

_kand_mask8 __mmask8 _kand_mask8(__mmask8 __A, __mmask8 __B)

AND r16/32/64, r16/32/64 Legacy -mavx512dq

_mm512_kand __mmask16 _mm512_kand(__mmask16 __A, __mmask16 __B)

AND r16/32/64, r16/32/64 Legacy -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More General-purpose instructions

All 109 General-purpose instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
  5. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.