AND

AND clears the bits of its destination that are clear in the source, usually a mask, and keeps the others.

Masks and immediates#

The immediate has at most 32 bits and is sign-extended to the operand size, which suits masks that clear low bits. GCC 14 and Clang 23 at -O2 compile aligning down to 16, x & -16, to and rax, -16 (4 bytes), and rounding up to lea rax, [rdi + 15] followed by the same AND. For an unsigned x, x % 8 is and eax, 7; a signed x needs a correction for negative values first.

A 64-bit mask with bits 63:32 clear cannot be a sign-extended immediate, but it needs none: a 32-bit AND clears those bits by writing a 32-bit register. Both compilers compile x & 0xfffffff0 on a uint64_t to a MOV and and eax, -16 (GCC prints the immediate as 4294967280), x & 0xffffffff to mov eax, edi and x & 0xff to MOVZX. Other wide masks, such as 0xffffffffff, are first loaded into a register with MOVABS.

Bit tricks#

• x & (x - 1) clears the lowest set bit: an LEA and an AND, or BLSR with BMI1 enabled (-mbmi).
• x & -x keeps only the lowest set bit: NEG and AND, or BLSI.
• ~a & b is NOT and AND, or ANDN, which also takes a separate destination.
• x & ~(1ul << n), clearing a bit whose number is in a register, becomes BTR in both compilers.

Testing bits#

AND sets ZF, SF and PF from the result and clears CF and OF, so a conditional jump can follow it directly, and newer processors fuse the pair. In Intel’s Optimization Reference Manual, Table 3-1 (Sandy Bridge) and Table 3-2 (Haswell) let AND, like TEST, fuse with every condition; AMD’s guide for Zen 5 lists AND among the instructions that fuse with a following branch (Section 2.9.3). When the result itself is not needed, Intel’s manual recommends TEST, which does the same AND without writing the destination (Coding Rule 36).

Atomic AND#

With LOCK and a memory destination, AND clears bits atomically: atomic_fetch_and compiles to lock and when its result is unused and to a CMPXCHG loop when it is used. AAND, from RAO-INT, does an atomic AND that is only weakly ordered with other memory accesses.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = dest & sext(src)             # with LOCK: one atomic read-modify-write;
                                 # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 (APX) leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

r = src1 & sext(src2)            # an immediate is sign-extended to OSIZE
if not nf:                       # NF=1 leaves the flags as they were
    of = cf = 0
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
dest.write(r)                    # the new destination: bits 63:OSIZE
                                 # cleared, even for 8 and 16 bits

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms

none in XED

EVEX forms

APX-EVEX-INT

Attributes

What else XED records about the forms. How to read.

AND m8, imm8 AND m8, r8 AND m16/32/64, imm16/32 AND m16/32/64, imm8 AND m16/32/64, r16/32/64

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions