ANDN

ANDN computes NOT a AND b into a third register, leaving both sources as they were: andn eax, esi, edi gives ~ESI & EDI. The inverted operand is the first source, the register in VEX.vvvv; only the second source may be in memory. Without BMI1 the same takes a copy, a NOT and an AND. The vector PANDN and ANDNPS also invert their first operand.

How compilers use it#

With -mbmi or -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile x & ~y to andn eax, esi, edi, with y, in ESI, as the inverted operand. Since ANDN sets ZF from its result, the test (x & ~y) == 0, which asks whether every bit of x is also set in y, becomes ANDN and SETE with no TEST between them.

Masks built at run time are another use: GCC 14 with -mbmi alone compiles (x >> s) & ((1ULL << n) - 1) to a shifted all-ones value and an ANDN that clears the field’s bits above n, where Clang 23 uses BEXTR; with BMI2 both use SHRX and BZHI instead.

What the flags say#

ANDN clears OF and CF and sets SF and ZF from the result, as AND does, but leaves PF and AF undefined, where AND defines PF. Code that needs the parity of the result must compute it some other way. APX adds an EVEX form that reaches its new registers and one that leaves the flags unchanged (NF).

Speed#

Intel’s optimization manual places ANDN among the instructions of the two bit-manipulation units of Golden Cove (Table 2-4). The instruction table of AMD’s Zen 5 guide lists ANDN as one macro-op with a latency of one cycle, on any of the integer ALUs.

ANDN belongs to BMI1, part of x86-64-v3.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = ~src1 & src2                 # src2 with the bits of src1 cleared
if not nf:                       # NF=1 (APX) leaves the flags as they were
    sf = msb(r)
    zf = r == 0
    of = cf = 0
    af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to ANDN, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI1 instructions

• BEXTR
• BLSI
• BLSMSK
• BLSR
• TZCNT

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions