ANDNPD instruction (SSE2)

ANDNPD inverts its first operand and ANDs the result with the second, 128 bits at a time: andnpd xmm0, xmm1 leaves NOT xmm0 AND xmm1 in XMM0. It is SSE2’s spelling for doubles of ANDNPS: the same bits with a 66 prefix, no rounding and no MXCSR flags. VANDNPS explains the order of the operands, which is easy to get backwards, and the VEX and EVEX forms; ANDPD covers the rest of the logic family on doubles. As a legacy SSE instruction, ANDNPD writes over its first operand, keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Since the inverted operand is also the destination, the value that gets inverted is the one that is lost. Zen 5’s recorded cases show the inversion acting on masks:

andnpd xmm12, xmm6, with XMM12 holding the absolute-value mask 7FFFFFFFFFFFFFFFh and -0.0 and XMM6 holding all ones and -0.0, gave 8000000000000000h and 0: the inverted mask keeps only the sign.
andnpd xmm8, xmmword ptr [mem], with -0.0 in XMM8 and the pattern 7FFFFFFFFFFFFFFFh in memory, gave that pattern back unchanged. It is a NaN as a double, and MXCSR stayed as it was.

Selecting with a compare

Without SSE4.1’s BLENDVPD, a choice between two vectors under a compare mask takes three logic instructions. In our builds at -O2 for the default target, Clang 23 vectorizes a[i] = b[i] < c[i] ? x : y (x and y loaded beforehand) to CMPLTPD, ANDPD of x with the mask, ANDNPD of the mask with y, and ORPD: the ANDNPD consumes the mask, so the compare result needs no copy. With -march=x86-64-v2 the three become one BLENDVPD. For a[i] = b[i] < c[i] ? 0.0 : t, Clang inverts the compare in the vector loop, CMPNLTPD and ANDPD, and keeps ANDNPD for the scalar tail, after CMPLTSD. GCC 14 keeps both loops scalar, with a branch on COMISD per element.

_mm_andnot_pd(a, b) inverts a. GCC compiles it to ANDNPD and Clang to ANDNPS, whose encoding is a byte shorter. For fabs and copysign, both use ANDPD or ANDPS with a constant mask rather than ANDNPD.

Forms

Every encoding of ANDNPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ANDNPD xmm, m128` ANDNPD_XMMxuq_MEMxuq	`66 0F 55 /r`	SSE2
`ANDNPD xmm, xmm` ANDNPD_XMMxuq_XMMxuq	`66 0F 55 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: ~a1&b1, ~a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = ~xmm1.q[i] & src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ANDNPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Selecting with a compare#