ANDNPS instruction (SSE)

ANDNPS inverts its first operand and ANDs the result with the second, 128 bits at a time: andnps xmm0, xmm1 leaves NOT xmm0 AND xmm1 in XMM0. Since the destination is the inverted operand, the value that is lost is the one that was inverted, typically a mask that is no longer needed. VANDNPS covers the order of the operands and the VEX and EVEX forms, and ANDPS the family’s bits-only nature: no rounding and no MXCSR flags. This legacy form came with the first SSE, keeps bits 128 and up of the register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes. ANDNPD is the double name, a byte longer.

In Zen 5’s recorded cases, andnps xmm4, xmmword ptr [mem] kept the one single whose pattern was 1 in memory and 0 in XMM4 and cleared the other three, and andnps xmm4, xmm4 gave zero from a register holding the patterns 0 and 1. AMD’s Zen 5 guide counts VANDNPS of a register with itself as a zeroing idiom but names no legacy form there (Section 2.9.2).

Three-instruction selects

Without SSE4.1’s BLENDVPS, choosing between two vectors under a compare mask takes ANDPS of one value with the mask, ANDNPS of the mask with the other, and ORPS. In our builds at -O2 for the default target, GCC 14 and Clang 23 compile a[i] = b[i] < c[i] ? 1.0f : 2.0f to exactly that after a CMPLTPS; with -march=x86-64-v2 both use one BLENDVPS. When one side is zero, one instruction remains:

b[i] < c[i] ? 0.0f : d[i] is CMPLTPS and ANDNPS in GCC, at both targets; Clang reverses the compare to CMPNLTPS and uses ANDPS.
On scalars, x < y ? 0.0f : z is CMPLTSS and ANDNPS in Clang.

ANDNPS also clears sign bits. With -0.0 as its first operand it computes fabsf, and GCC uses it that way inside copysignf and -fabsf(x), followed by ORPS. Clang compiles the integer b[i] & ~c[i] to ANDNPS as well, where GCC needs three instructions (see PANDN).

In the optimization guide

What the optimization guide says about ANDNPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Jaguar and Puma

Integer execution: xor, sub and cmp of a register with itself, and pxor, pandn, psub*, pcmpeq*, pcmpgt*, xorps and xorpd likewise, do not wait for the old value, and sbb waits only for the carry; ANDNPS and ANDNPD join them on Jaguar.

Forms

Every encoding of ANDNPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ANDNPS xmm, m128` ANDNPS_XMMxud_MEMxud	`NP 0F 55 /r`	SSE
`ANDNPS xmm, xmm` ANDNPS_XMMxud_XMMxud	`NP 0F 55 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: ~a3&b3, ~a2&b2, ~a1&b1, ~a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = ~xmm1.d[i] & src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ANDNPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Three-instruction selects#