ANDPD instruction (SSE2)

ANDPD is the bitwise AND of two 128-bit values, SSE2’s spelling for doubles of the ANDPS operation: the bits are the same, nothing is rounded and MXCSR plays no part. VANDPD covers the uses (absolute values, copied signs, a compare result selecting elements) and the VEX and EVEX forms. As a legacy SSE instruction, it writes over its first operand, keeps bits 128 and up of the register (see SSE and AVX) and needs its memory operand aligned to 16 bytes. Its encoding is ANDPS’s with a 66 prefix, one byte longer.

Zen 5’s recorded cases show bits, not numbers: two denormals, 15 and 16 times 2^-1074 as bit patterns, ANDed with 1 gave 1 and 0, and -0 ANDed with an all-ones NaN stayed -0.

Scalars too

SSE has no scalar AND, so code on one double uses the packed instruction on the whole register. In our builds at -O2, with the default target and with -march=x86-64-v2, GCC 14 compiles fabs(x) to andpd xmm0, XMMWORD PTR .LC0[rip], a 16-byte constant in the low half 7FFFFFFFFFFFFFFFh and zero above it, aligned to 16 bytes so that the memory form may read it. copysign(x, y) is two ANDPDs and an ORPD. Clang 23 emits ANDPS for the same code, and for loops over arrays of doubles too, and keeps ANDPD next to compares on doubles. b[i] < c[i] ? b[i] : 0.0 is CMPLTPD and ANDPD in Clang, the compare’s all-ones elements keeping b and its zeros clearing it; GCC keeps that loop scalar, with CMPLTSD and ANDPD on each element.

Forms

Every encoding of ANDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ANDPD xmm, m128` ANDPD_XMMxuq_MEMxuq	`66 0F 54 /r`	SSE2
`ANDPD xmm, xmm` ANDPD_XMMxuq_XMMxuq	`66 0F 54 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each quadword of the result comes from the quadword in the same place in each source.

Result quadword i comes from quadword i of xmm1 and xmm2. Result quadwords 1 to 0: a1&b1, a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = xmm1.q[i] & src2.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ANDPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Scalars too#