ANDPS instruction (SSE)

ANDPS is the bitwise AND of two 128-bit values, read as four singles but treated as bits: nothing is rounded, MXCSR plays no part and NaNs and denormals pass through untouched. VANDPS covers its uses with masks (absolute values, copied signs, a compare result selecting elements) and the VEX and EVEX forms; ANDNPS, ORPS and XORPS complete the family, and ANDPD is the same bits under a double name. This legacy form came with the first SSE, writes over its first operand, keeps bits 128 and up of the register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes.

On Zen 5, the recorded andps xmm8, xmmword ptr [mem] ANDed -0 with 7FFFFFFFh, the absolute-value mask, into +0, and turned the denormals 15 and 16 times 2^-149, ANDed with 1, into 1 and 0, leaving MXCSR at 1F80h with no flag set. andps xmm4, xmm4 left a register holding an all-ones NaN as it was.

Scalars and the shortest AND

SSE has no scalar AND, so code on one float uses the packed instruction on the whole register. In our builds at -O2, with the default target and with -march=x86-64-v2:

fabsf(x) is andps xmm0, XMMWORD PTR .LC0[rip] in GCC 14 and Clang 23, a 16-byte constant aligned so that the memory form may read it. In a loop, GCC builds the mask in a register with MOVSS and SHUFPS, and Clang loads it whole.
x < y ? 0.0f : z on scalars is CMPNLTSS and ANDPS in GCC, the reversed compare keeping z; Clang uses CMPLTSS and ANDNPS.
b[i] < c[i] ? b[i] : 0.0f over arrays is CMPPS with the less-than predicate and ANDPS in both.

Having no prefix, ANDPS is a byte shorter than PAND and ANDPD, and Clang uses it for other data too: for an integer b[i] & c[i] whose result is only stored, and for fabs on doubles. AMD’s Zen 5 guide nonetheless asks for instructions that match the data type of their inputs (Section 2.11.2), and its latency spreadsheet gives ANDPS, like PAND, one cycle and four per cycle.

Forms

Every encoding of ANDPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ANDPS xmm, m128` ANDPS_XMMxud_MEMxud	`NP 0F 54 /r`	SSE
`ANDPS xmm, xmm` ANDPS_XMMxud_XMMxud	`NP 0F 54 /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: a3&b3, a2&b2, a1&b1, a0&b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = xmm1.d[i] & src2.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ANDPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Scalars and the shortest AND#