AOR instruction (RAO-INT, APX)

AOR ORs a general-purpose register into a doubleword or quadword in memory atomically and returns nothing: the bitwise OR among RAO-INT’s remote atomic operations, encoded as F2 0F38 FC, where AADD has no prefix. AADD’s page covers what they share: a naturally aligned destination in write-back memory, or #GP; #UD with a LOCK prefix; no flags; the weak ordering of write-combining stores, which a following SFENCE or MFENCE strengthens; and Intel’s advice on when remote updates pay.

Setting bits that only get set

OR fits marks that many cores add and nobody removes during a phase: visited nodes of a graph, pages seen dirty, bits of a Bloom filter. The result does not depend on the order of the updates, and setting a bit twice changes nothing, so the weak ordering costs nothing until the phase ends with a fence and the bits are read. To learn whether a bit was already set, code needs lock with BTS instead, as the page of OR shows for atomic_fetch_or.

In our builds and on Zen 5

GCC 14 and Clang 23 at -O2 with -mraoint compile _aor_i32(&c, v) to aor dword ptr [rip + c], edi (GCC writes DWORD PTR c[rip]), and _aor_i64 gives the quadword form. The Zen 5 behind this site’s recorded cases lacks RAO-INT, CPUID.(EAX=07H,ECX=1):EAX[3], and both cases, aor dword ptr [0x10000008], ecx and the quadword form, raised #UD.

Forms

Every encoding of AOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AOR m32, r32` AOR_MEM32_GPR32	`F2 0F 38 FC /r`	RAO_INT
`AOR m64, r64` 64-bit mode only AOR_MEM64_GPR64	`F2 REX.W 0F 38 FC /r`	RAO_INT
`AOR m32, r32` AOR_MEMi32_GPR32i32_APX	`EVEX.LLZ.F2.MAP4.W0 FC /r`	APX_F + RAO_INT
`AOR m64, r64` AOR_MEMi64_GPR64i64_APX	`EVEX.LLZ.F2.MAP4.W1 FC /r`	APX_F + RAO_INT

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 3 & 1:
    fault(UD)                    # CPUID: no RAO-INT
dest.write(dest | src)           # one atomic read-modify-write, weakly
                                 # ordered, unlike LOCK OR: #GP(0) unless
                                 # dest is aligned to its size and in
                                 # write-back memory; no flag changes

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no RAO-INT, and every one raised an exception. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AOR m32, r32` `AOR m64, r64` 64-bit mode only
`m32/64`	explicit	read, write
`r32/64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms: LEGACY-RAO-INT
EVEX forms: APX-EVEX-RAO-INT

Attributes

What else XED records about the forms. How to read.

All forms: always atomic; may abort a TSX transaction
AOR m32, r32: 4-byte aligned memory operand
AOR m64, r64 64-bit mode only: 8-byte aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to AOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_aor_i32` `void _aor_i32(int *__A, int __B)`	`AOR m32, r32` Legacy -mraoint
`_aor_i64` `void _aor_i64(long long *__A, long long __B)`	`AOR m64, r64` Legacy -mraoint

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`RAO_INT` RAO-INT	RAO_INT `CPUID.(EAX=07H,ECX=1):EAX[3]` RAO_INT	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`APX_F_RAO_INT` APX	APX_F + RAO_INT `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=1):EAX[3]` RAO_INT	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More RAO-INT instructions

More APX instructions

All 88 APX instructions

Setting bits that only get set#

In our builds and on Zen 5#