ARPL instruction (System)

Forms

Every encoding of ARPL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`ARPL m16, r16` not in 64-bit mode ARPL_MEMw_GPR16	`63 /r`	Base instruction set
`ARPL r16, r16` not in 64-bit mode ARPL_GPR16_GPR16	`63 /r`	Base instruction set

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

d = dest.read()                  # two selectors
if d & 3 < src & 3:
    dest.write(d & ~3 | src & 3) # raises dest's RPL to src's
    zf = 1
else:
    zf = 0                       # dest is not written

Not run on a processor: ARPL does not exist in 64-bit mode, where the probe runs: its opcode, 63, is MOVSXD there.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`ARPL r/m16, r16` not in 64-bit mode
`r/m16`	explicit	read, write
`r16`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified; blank: not affected. How to read.

ZF
All forms
M

Attributes

What else XED records about the forms. How to read.

All forms: not in real-address mode

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I286PROTECTED` System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

ARPL