x86-64.net

Instruction

AXOR

Atomically XORs a register into a naturally aligned 32- or 64-bit value in memory without returning anything, as a weakly ordered remote atomic operation.

Extensions
Forms
4 (2 Legacy, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of AXOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
AXOR m32, r32 AXOR_MEM32_GPR32F3 0F 38 FC /rRAO_INT
AXOR m64, r64 64-bit mode only AXOR_MEM64_GPR64F3 REX.W 0F 38 FC /rRAO_INT
AXOR m32, r32 AXOR_MEMi32_GPR32i32_APXEVEX.LLZ.F3.MAP4.W0 FC /rAPX_F + RAO_INT
AXOR m64, r64 AXOR_MEMi64_GPR64i64_APXEVEX.LLZ.F3.MAP4.W1 FC /rAPX_F + RAO_INT

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to AXOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_axor_i32 void _axor_i32(int *__A, int __B)

AXOR m32, r32 Legacy -mraoint

_axor_i64 void _axor_i64(long long *__A, long long __B)

AXOR m64, r64 Legacy -mraoint

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
RAO_INT

RAO_INT
CPUID.(EAX=07H,ECX=1):EAX[3] RAO_INT

None yet: XED lists these instructions only under its placeholder for future processors.
APX_F_RAO_INT

APX_F + RAO_INT
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EAX[3] RAO_INT

None yet: XED lists these instructions only under its placeholder for future processors.

More RAO-INT instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.