AXOR instruction (RAO-INT, APX)

AXOR XORs a general-purpose register into a doubleword or quadword in memory atomically and returns nothing: the bitwise XOR among RAO-INT’s remote atomic operations, encoded as F3 0F38 FC, where AADD has no prefix. AADD’s page covers what they share: a naturally aligned destination in write-back memory, or #GP; #UD with a LOCK prefix; no flags; the weak ordering of write-combining stores, which a following SFENCE or MFENCE strengthens; and Intel’s advice on when remote updates pay.

Toggling and folding

XOR flips the bits set in its source, so AXOR with a mask toggles them, and two updates with the same mask cancel. Like addition, XOR gives the same result in any order of its updates, which suits accumulating a checksum or a parity word over data that several cores process: each core folds its part into the shared word and a fence at the end makes the total visible. XOR is also its own inverse: XORing an entry’s hash into a set’s fingerprint adds the entry, and the same AXOR again removes it, where AADD needs the negated value to undo an addition. XOR is the ordinary form, which takes a LOCK prefix for a strongly ordered atomic update.

In our builds and on Zen 5

GCC 14 and Clang 23 at -O2 with -mraoint compile _axor_i64(&c, v) to axor qword ptr [rip + c], rdi (GCC writes QWORD PTR c[rip]), and _axor_i32 gives the doubleword form. The Zen 5 behind this site’s recorded cases lacks RAO-INT, CPUID.(EAX=07H,ECX=1):EAX[3], and both cases, axor dword ptr [0x10000008], ecx and the quadword form, raised #UD.

Forms

Every encoding of AXOR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`AXOR m32, r32` AXOR_MEM32_GPR32	`F3 0F 38 FC /r`	RAO_INT
`AXOR m64, r64` 64-bit mode only AXOR_MEM64_GPR64	`F3 REX.W 0F 38 FC /r`	RAO_INT
`AXOR m32, r32` AXOR_MEMi32_GPR32i32_APX	`EVEX.LLZ.F3.MAP4.W0 FC /r`	APX_F + RAO_INT
`AXOR m64, r64` AXOR_MEMi64_GPR64i64_APX	`EVEX.LLZ.F3.MAP4.W1 FC /r`	APX_F + RAO_INT

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 3 & 1:
    fault(UD)                    # CPUID: no RAO-INT
dest.write(dest ^ src)           # one atomic read-modify-write, weakly
                                 # ordered, unlike LOCK XOR: #GP(0) unless
                                 # dest is aligned to its size and in
                                 # write-back memory; no flag changes

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no RAO-INT, and every one raised an exception. The APX forms were not run: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`AXOR m32, r32` `AXOR m64, r64` 64-bit mode only
`m32/64`	explicit	read, write
`r32/64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Legacy forms: LEGACY-RAO-INT
EVEX forms: APX-EVEX-RAO-INT

Attributes

What else XED records about the forms. How to read.

All forms: always atomic; may abort a TSX transaction
AXOR m32, r32: 4-byte aligned memory operand
AXOR m64, r64 64-bit mode only: 8-byte aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to AXOR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_axor_i32` `void _axor_i32(int *__A, int __B)`	`AXOR m32, r32` Legacy -mraoint
`_axor_i64` `void _axor_i64(long long *__A, long long __B)`	`AXOR m64, r64` Legacy -mraoint

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`RAO_INT` RAO-INT	RAO_INT `CPUID.(EAX=07H,ECX=1):EAX[3]` RAO_INT	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.
`APX_F_RAO_INT` APX	APX_F + RAO_INT `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=07H,ECX=1):EAX[3]` RAO_INT	None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More RAO-INT instructions

More APX instructions

All 88 APX instructions

Toggling and folding#

In our builds and on Zen 5#