BEXTR

BEXTR copies a field of bits from its source to the low bits of the destination and clears the rest. A control register gives the field: its bits 7:0 the field’s lowest bit, its bits 15:8 the number of bits, and the bits above them do not count. To take bits 11:7 of EAX, the control is 0x0507: bextr ecx, eax, edx with EDX = 0x0507 puts them in bits 4:0 of ECX.

The control’s edges are defined, unlike C’s shifts by the operand width or more: a length of 0 gives 0, a start past the top of the operand gives 0, and a field that runs past the top is filled with zeros there.

Rarely chosen by compilers#

The control must be built in a register, which costs as much as the shift and AND it replaces. So GCC 14 and Clang 23 at -O2, even with -march=x86-64-v3, compile a constant field such as (x >> 7) & 0x1F to SHR and AND, and a variable field with BMI2 to SHRX and BZHI. With -mbmi alone, Clang 23 builds the control from s and n with a shift and an OR and uses BEXTR for (x >> s) & ((1ULL << n) - 1); GCC 14 builds a mask for ANDN. The intrinsic _bextr_u64(x, start, len) also packs the control first; _bextr2_u64(x, control) takes one ready-made.

What the flags say#

ZF tells whether the field was zero. The manuals clear CF and OF, while XED leaves them undefined; Zen 5 cleared both in every recorded case, as the page’s pseudocode and its note on Intel’s documentation say. SF, AF and PF are undefined.

AMD’s immediate form#

AMD’s TBM extension, from the Piledriver generation, added a BEXTR whose control is a 32-bit immediate, in the XOP encoding. Zen 5 has no TBM: it raised #UD for each of these forms. Code that needs a constant field on current processors uses a shift and an AND.

Speed#

The instruction table of AMD’s Zen 5 guide lists BEXTR as one macro-op with a latency of one cycle; Intel’s optimization manual places it among the instructions of the two bit-manipulation units of Golden Cove (Table 2-4).

BEXTR belongs to BMI1, part of x86-64-v3; APX adds an EVEX form and one that leaves the flags unchanged (NF).

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

start = control & 0xFF           # bits 7:0: the field's lowest bit
length = control >> 8 & 0xFF     # bits 15:8: its number of bits
r = src >> start & (1 << length) - 1   # bits past the top of src read
                                       # as 0, so a start of OSIZE or
                                       # more gives 0
if not nf:                       # NF=1 (APX) leaves the flags as they were
    zf = r == 0
    of = cf = 0
    sf = af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

features = cpuid_leaf(0x80000001, 0)[2]
if not features >> 21 & 1:
    fault(UD)                    # CPUID: no TBM
start = control & 0xFF           # imm32 bits 7:0: the field's lowest bit
length = control >> 8 & 0xFF     # bits 15:8: its number of bits; bits
                                 # 31:16 are ignored
r = src >> start & (1 << length) - 1   # bits past the top of src read
                                       # as 0
zf = r == 0
of = cf = 0
sf = af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX and XOP forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BEXTR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI1 instructions

• ANDN
• BLSI
• BLSMSK
• BLSR
• TZCNT

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions

More TBM instructions

• BLCFILL
• BLCI
• BLCIC
• BLCMSK
• BLCS
• BLSFILL
• BLSIC
• T1MSKC
• TZMSK