x86-64.net

Instruction

BEXTR

Extracts a bit field whose start and length come from a second register; APX adds a form that leaves the flags unchanged.

Extensions
Forms
16 (4 VEX, 8 EVEX, 4 XOP)
Data
Intel XED v2026.08.23

Forms

Every encoding of BEXTR that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BEXTR r32, m32, r32 BEXTR_GPR32d_MEMd_GPR32dVEX.LZ.NP.0F38.W0 F7 /rBMI1
BEXTR r32, r32, r32 BEXTR_GPR32d_GPR32d_GPR32dVEX.LZ.NP.0F38.W0 F7 /rBMI1
BEXTR r64, m64, r64 64-bit mode only BEXTR_GPR64q_MEMq_GPR64qVEX.LZ.NP.0F38.W1 F7 /rBMI1
BEXTR r64, r64, r64 64-bit mode only BEXTR_GPR64q_GPR64q_GPR64qVEX.LZ.NP.0F38.W1 F7 /rBMI1
BEXTR r32, r32, r32 BEXTR_GPR32i32_GPR32i32_GPR32i32_APXEVEX.LLZ.NP.0F38.W0 F7 /rAPX_F + BMI1
BEXTR r32, m32, r32 BEXTR_GPR32i32_MEMi32_GPR32i32_APXEVEX.LLZ.NP.0F38.W0 F7 /rAPX_F + BMI1
BEXTR r32, r32, r32 NF BEXTR_GPR32i32_GPR32i32_GPR32i32_APX_N3EVEX.LLZ.NP.0F38.W0 F7 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1
BEXTR r32, m32, r32 NF BEXTR_GPR32i32_MEMi32_GPR32i32_APX_N3EVEX.LLZ.NP.0F38.W0 F7 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1
BEXTR r64, r64, r64 BEXTR_GPR64i64_GPR64i64_GPR64i64_APXEVEX.LLZ.NP.0F38.W1 F7 /rAPX_F + BMI1
BEXTR r64, m64, r64 BEXTR_GPR64i64_MEMi64_GPR64i64_APXEVEX.LLZ.NP.0F38.W1 F7 /rAPX_F + BMI1
BEXTR r64, r64, r64 NF BEXTR_GPR64i64_GPR64i64_GPR64i64_APX_N3EVEX.LLZ.NP.0F38.W1 F7 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1
BEXTR r64, m64, r64 NF BEXTR_GPR64i64_MEMi64_GPR64i64_APX_N3EVEX.LLZ.NP.0F38.W1 F7 /r NF=1APX_F + APX_NCI_NDD_NF + BMI1
BEXTR r32, m32, imm32 not in 64-bit mode BEXTR_XOP_GPR32d_MEMd_IMMdXOP.LZ.NP.0A.WIG 10 /r idBase instruction set
BEXTR r32/64, m32/64, imm32 64-bit mode only BEXTR_XOP_GPRyy_MEMy_IMMdXOP.LZ.NP.0A.WIG 10 /r idBase instruction set
BEXTR r32, r32, imm32 not in 64-bit mode BEXTR_XOP_GPR32d_GPR32d_IMMdXOP.LZ.NP.0A.WIG 10 /r idBase instruction set
BEXTR r32/64, r32/64, imm32 64-bit mode only BEXTR_XOP_GPRyy_GPRyy_IMMdXOP.LZ.NP.0A.WIG 10 /r idBase instruction set

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BEXTR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_bextr2_u32 unsigned int _bextr2_u32(unsigned int __X, unsigned int __Y)

BEXTR r32, r32, r32 VEX.LZ -mbmi

_bextr2_u64 unsigned long long _bextr2_u64(unsigned long long __X, unsigned long long __Y)

BEXTR r64, r64, r64 VEX.LZ -mbmi

__bextr_u32 unsigned int __bextr_u32(unsigned int __X, unsigned int __Y)

BEXTR r32, r32, r32 VEX.LZ -mbmi

__bextr_u64 unsigned long long __bextr_u64(unsigned long long __X, unsigned long long __Y)

BEXTR r64, r64, r64 VEX.LZ -mbmi

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
BMI1

BMI1
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's Piledriver adds TBM and FMA to Bulldozer but not BMI1, and its Zen chips inherit that gap; GCC's -march=bdver2 and -march=znver1 and later include BMI1.

APX_F_BMI1

APX_F + BMI1
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Nova Lake, Diamond Rapids
APX_F_BMI1_N3

APX_F + APX_NCI_NDD_NF + BMI1
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=0):EBX[3] BMI1

Nova Lake, Diamond Rapids
TBM

No CPUID bit: part of the base instruction set.

Piledriver, Zen, Zen+, Zen 2

Note: XED's Zen chips inherit TBM from its Piledriver chip; GCC's -march=znver1 and later do not enable TBM.

More BMI1 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.