BLENDPD instruction (SSE4.1)

BLENDPD picks each of the two doubles of its result by a constant: bit 0 of the immediate set takes element 0 from the second operand, bit 1 element 1, and a clear bit keeps the destination’s own. The other six bits are ignored. VBLENDPD describes the operation in its VEX form, with a separate destination and a 256-bit form; BLENDVPD chooses at run time by the sign bits of XMM0. BLENDPD came with SSE4.1, so it needs -march=x86-64-v2 or -msse4.1; like other legacy SSE instructions it writes over its first operand, keeps bits 128 and up of the register (see SSE and AVX), and wants a memory operand aligned to 16 bytes, although it may use only half of it.

Zen 5’s recorded cases follow bits 1:0 alone: blendpd xmm0, xmmword ptr [mem], 0x46 and blendpd xmm7, xmm11, 0x2a, both with 10b there, kept element 0 of the destination and took element 1 from the source, whatever bits 7:2 held.

Rarely emitted

With two elements, a blend is also a shuffle or a merging move, and our compilers prefer those. In our builds at -O2 with -march=x86-64-v2, GCC 14 compiles _mm_blend_pd(a, b, 1) to movsd xmm0, xmm1 and _mm_blend_pd(a, b, 2) to shufpd xmm0, xmm1, 2 (SHUFPD); with b read from memory, it loads only the high half, with MOVHPS. Clang 23 writes all three as BLENDPS, with 3 or 12 as its immediate, each bit of the double blend doubled. Neither emitted BLENDPD for these, nor for a loop that takes the even elements from one array and the odd ones from another, which both built from a MOVSD and a MOVHPD load.

On Zen 5 the substitute is no worse: AMD’s latency spreadsheet lists BLENDPD on two of the four vector pipes, FP0 and FP1, and BLENDPS and SHUFPD on all four, with a latency of 1 cycle for each.

Forms

Every encoding of BLENDPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`BLENDPD xmm, m128, imm8` BLENDPD_XMMdq_MEMdq_IMMb	`66 0F 3A 0D /r ib`	SSE4.1
`BLENDPD xmm, xmm, imm8` BLENDPD_XMMdq_XMMdq_IMMb	`66 0F 3A 0D /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by immediate: each double comes from xmm2 where its bit of imm8 is 1, else from xmm1.

Example: imm8 = 0x01 (0000 0001 in binary).

Result doubles 1 to 0: a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    if imm8 >> i & 1:
        xmm1.q[i] = src2.q[i]
    else:
        xmm1.q[i] = xmm1.q[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`BLENDPD xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLENDPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blend_pd` `__m128d _mm_blend_pd(__m128d V1, __m128d V2, const int M)`	`BLENDPD xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Rarely emitted#