BLENDPS instruction (SSE4.1)

BLENDPS takes each of four singles from its source where the matching bit of the immediate is set, and keeps the destination’s own element where it is clear; only bits 3:0 count. VBLENDPS describes the operation and its 256-bit VEX form, and BLENDVPS makes the choice at run time from sign bits. BLENDPS came with SSE4.1, so it needs -march=x86-64-v2 or -msse4.1; as a legacy SSE instruction it writes over its first operand, keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

Zen 5’s recorded cases ignored the upper nibble: blendps xmm8, xmmword ptr [mem], 0xed took elements 0, 2 and 3 from memory and kept element 1, and blendps xmm1, xmm2, 0x8a took elements 1 and 3 from XMM2.

Which operand to overwrite

A blend can be written either way round: swapping the two operands and inverting the immediate gives the same result. With two operands that choice decides which register is overwritten. In our builds at -O2 with -march=x86-64-v2, __builtin_shufflevector(a, b, 0, 5, 2, 7) on two __m128 values is blendps xmm0, xmm1, 10 in Clang 23, written straight into the return register, while GCC 14 blends the other way round, blendps xmm1, xmm0, 5, and needs a MOVAPS to move the result to XMM0. Setting element 0, a[0] = x, is blendps xmm0, xmm1, 1 in Clang and a MOVSS between registers, the same merge, in GCC. For the default target, without SSE4.1, both compilers build that shuffle from two SHUFPS. Clang also blends doubles with BLENDPS, as BLENDPD’s page shows.

AMD’s spreadsheet for Zen 5 lists BLENDPS as one macro-op with a latency of 1 cycle on all four vector pipes, where the variable BLENDVPS uses two.

Forms

Every encoding of BLENDPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`BLENDPS xmm, m128, imm8` BLENDPS_XMMdq_MEMdq_IMMb	`66 0F 3A 0C /r ib`	SSE4.1
`BLENDPS xmm, xmm, imm8` BLENDPS_XMMdq_XMMdq_IMMb	`66 0F 3A 0C /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by immediate: each single comes from xmm2 where its bit of imm8 is 1, else from xmm1.

Example: imm8 = 0x05 (0000 0101 in binary).

Result singles 3 to 0: a3, b2, a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    if imm8 >> i & 1:
        xmm1.d[i] = src2.d[i]
    else:
        xmm1.d[i] = xmm1.d[i]
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`BLENDPS xmm, xmm/m128, imm8`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLENDPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blend_ps` `__m128 _mm_blend_ps(__m128 V1, __m128 V2, const int M)`	`BLENDPS xmm, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Which operand to overwrite#