BLENDVPD instruction (SSE4.1)

BLENDVPD picks each of two doubles from its source where bit 63 of the matching quadword of XMM0 is set, and keeps the destination’s own double elsewhere. BLENDVPS explains the implied XMM0 and what a floating-point mask means, PBLENDVB how compilers steer a mask into XMM0, and VBLENDVPD is the VEX form, which names the mask as a fourth register. BLENDVPD came with SSE4.1 (-march=x86-64-v2); as a legacy SSE instruction it keeps bits 128 and up of the register (see SSE and AVX) and needs a memory operand aligned to 16 bytes.

XMM0 may be the destination as well as the mask. Zen 5’s recorded blendvpd xmm0, xmmword ptr [mem], with a negative double below and a positive one above in XMM0, took the low double from memory and kept the high one, and blendvpd xmm7, xmm11 under the same XMM0 replaced only the low double of XMM7.

Integers by their sign

For a 64-bit integer, the sign bit is the whole of the test x < 0. In our builds at -O2 with -march=x86-64-v2, GCC 14 and Clang 23 compile r[i] = x[i] < 0 ? x[i] : y[i] over long long arrays to BLENDVPD with the data as its own mask, blendvpd xmm1, xmm0, xmm0, and no compare. When the mask comes from a third array, GCC compares with PCMPGTQ and blends with PBLENDVB, and Clang keeps the loop scalar with CMOVS. For doubles the sign bit is not enough, since -0.0 and a NaN with its sign set are not less than zero: GCC compares with CMPLTPD first, and for p[i] > q[i] ? p[i] : 0.5 both compilers use CMPLTPD and BLENDVPD, copying the vector of halves before each blend, which overwrites it.

AMD’s spreadsheet for Zen 5 lists BLENDVPD as one macro-op with a latency of 1 cycle on pipes FP0 and FP1, two per cycle.

Forms

Every encoding of BLENDVPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`BLENDVPD xmm, m128` BLENDVPD_XMMdq_MEMdq	`66 0F 38 15 /r`	SSE4.1
`BLENDVPD xmm, xmm` BLENDVPD_XMMdq_XMMdq	`66 0F 38 15 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by vector: each double comes from xmm2 where the sign bit of the double in the same place of XMM0 is 1, else from xmm1.

Example sign bits of XMM0: 01.

Result doubles 1 to 0: a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    if xmm0.q[i] >> 63:
        xmm1.q[i] = src2.q[i]
    else:
        xmm1.q[i] = xmm1.q[i]
# xmm0.q[i] >> 63: the sign bit of the element
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`BLENDVPD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`XMM0`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLENDVPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blendv_pd` `__m128d _mm_blendv_pd(__m128d __V1, __m128d __V2, __m128d __M)`	`BLENDVPD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Integers by their sign#