BLENDVPS instruction (SSE4.1)

BLENDVPS picks each of four singles from one of two vectors: where the sign bit of the matching element of XMM0 is set, the source’s element replaces the destination’s; elsewhere the destination keeps its own. It is the doubleword version of PBLENDVB, which explains the implied XMM0 operand and how compilers steer a mask into it; this page is about what a float mask means.

Sign bits, not comparisons

Only bit 31 of each mask element counts. A comparison such as CMPPS gives all ones or all zeros per element, so its result works as a mask directly. Using the data itself as the mask is not the same as testing it: -0.0 and a NaN with its sign bit set both select, although neither is less than zero. So for r[i] = c[i] < 0 ? a[i] : b[i] over float arrays, GCC 14 at -O2 with -msse4.1 compares first, CMPLTPS of c against a zeroed register, then a BLENDVPS that reads a from memory. For an int array with the same test, the sign bit alone would do, yet GCC still compares, with PCMPGTD. Clang 23 kept both loops scalar, with a branch per element, as the C code reads only one of the two arrays per element; with both operands computed unconditionally, as in a[i] > b[i] ? a[i] : 0.5f, it vectorizes to CMPLTPS and BLENDVPS like GCC.

The intrinsic is _mm_blendv_ps(a, b, mask), which takes b where the mask is set. Without SSE4.1, GCC blends the same loop with ANDPS, ANDNPS and ORPS.

The other blends

BLENDPS takes its choice from an immediate, fixed when the code is assembled; BLENDVPD uses the sign bit of each quadword.
VBLENDVPS, the VEX form, names the mask as a fourth register, has a 256-bit form and leaves its sources intact.
AVX-512 has no EVEX form: compares there write mask registers, and VBLENDMPS or masking on any instruction selects under them.

The instruction table of AMD’s Zen 5 guide lists BLENDVPS and VBLENDVPS as one macro-op with a latency of one cycle, on two of the four vector pipes, where BLENDPS can use all four. The legacy form needs a memory operand aligned to 16 bytes.

Forms

Every encoding of BLENDVPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`BLENDVPS xmm, m128` BLENDVPS_XMMdq_MEMdq	`66 0F 38 14 /r`	SSE4.1
`BLENDVPS xmm, xmm` BLENDVPS_XMMdq_XMMdq	`66 0F 38 14 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Blend by vector: each single comes from xmm2 where the sign bit of the single in the same place of XMM0 is 1, else from xmm1.

Example sign bits of XMM0: 0101.

Result singles 3 to 0: a3, b2, a1, b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    if xmm0.d[i] >> 31:
        xmm1.d[i] = src2.d[i]
    else:
        xmm1.d[i] = xmm1.d[i]
# xmm0.d[i] >> 31: the sign bit of the element
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`BLENDVPS xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read
`XMM0`	implicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLENDVPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_blendv_ps` `__m128 _mm_blendv_ps(__m128 __V1, __m128 __V2, __m128 __M)`	`BLENDVPS xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Sign bits, not comparisons#

The other blends#