BLSI

BLSI keeps only the lowest set bit of its source: for 0x28 it gives 0x8, and for 0 it gives 0. It is the C idiom x & -x in one instruction, and with -mbmi or -march=x86-64-v3 GCC 14 and Clang 23 at -O2 compile that idiom to blsi eax, edi. The result is a mask, not an index: TZCNT gives the bit’s position, BLSR clears the bit instead of keeping it, and BLSMSK sets every bit up to and including it.

The flags tell zero apart#

ZF is set when the result is 0, which happens only for a zero source. CF is the other way round: both vendors’ manuals describe BLSI as a NEG followed by an AND and take CF from the NEG, so CF is set for any nonzero source and cleared for zero. Zen 5 did exactly that in every recorded case. XED records CF as always cleared, which the page’s note on Intel’s documentation points out; code that relies on CF should follow the manuals. SF copies the result’s top bit, OF is cleared, and AF and PF are undefined.

Uses#

Taking the lowest set bit as a mask suits code that works on sets of bits: removing a handled element with an XOR, or a Fenwick tree, whose index steps are i += i & -i and i -= i & -i. Where a loop needs the index of each bit, TZCNT with BLSR is the usual pair.

A false dependency on Zen 5#

AMD’s Zen 5 guide says that some versions of Zen 5 make BLSI, BLSR, BLSMSK and TZCNT wait for the old value of their destination register, which they do not read, and suggests zeroing the destination with an XOR before them (Section 2.9.9). Its instruction table lists BLSI as one macro-op with a latency of one cycle.

BLSI belongs to BMI1, part of x86-64-v3; APX adds an EVEX form and one that leaves the flags unchanged (NF).

In the optimization guide

What the optimization guide says about BLSI, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 5

• Integer execution: Some versions of Zen 5 make TZCNT, BLSI, BLSR and BLSMSK wait for the old value of their destination.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = src.read()
r = s & -s                       # the lowest 1 bit alone
if not nf:                       # NF=1 (APX) leaves the flags as they were
    cf = s != 0
    sf = msb(r)
    zf = r == 0
    of = 0
    af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLSI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI1 instructions

• ANDN
• BEXTR
• BLSMSK
• BLSR
• TZCNT

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions