BLSMSK

BLSMSK sets every bit from bit 0 up to and including the lowest set bit of its source, and clears the rest: for 0x28 it gives 0xF, for 1 it gives 1. It is the C idiom x ^ (x - 1) in one instruction, and with -mbmi or -march=x86-64-v3 GCC 14 and Clang 23 at -O2 compile that idiom to blsmsk eax, edi. Of its BMI1 siblings, BLSI keeps the lowest set bit alone and BLSR clears it; BLSMSK’s result is BLSI’s times two, minus one.

A source of zero#

With no bit set there is no lowest one, and BLSMSK returns all ones: Zen 5 gave FFFFFFFFH for a zero 32-bit source and FFFFFFFFFFFFFFFFH for a zero 64-bit one. CF tells that case apart, as it is set only for a zero source. ZF is always cleared, since the result always has bit 0 set, so ZF says nothing here, unlike after BLSI and BLSR. SF copies the result’s top bit, which is set only when the source is zero or its lowest set bit is the top one, and OF is cleared.

Both manuals leave AF and PF undefined. In every recorded case Zen 5 cleared AF and set PF from the low byte of the result, but code should not rely on either.

Uses#

A mask from a compare, such as the one PMOVMSKB makes from a PCMPEQB with one bit per byte, often needs everything up to and including the first match: BLSMSK gives it in one step. The related masks have no BMI1 instruction. ~x & (x - 1), the trailing zeros alone, compiles to LEA and ANDN, and x | (x - 1), which fills them in, to LEA and OR. AMD’s TBM extension has single instructions for both, TZMSK and BLSFILL.

Speed#

AMD’s Zen 5 instruction table lists BLSMSK as one macro-op with a latency of one cycle, three per cycle. The guide’s warning about a false dependency on the destination in some versions of Zen 5, which the BLSI page describes, names BLSMSK too (Section 2.9.9). BLSMSK belongs to BMI1, part of x86-64-v3; APX adds an EVEX form and one that leaves the flags unchanged (NF).

In the optimization guide

What the optimization guide says about BLSMSK, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 5

• Integer execution: Some versions of Zen 5 make TZCNT, BLSI, BLSR and BLSMSK wait for the old value of their destination.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = src.read()
r = low(s ^ (s - 1))             # ones up to the lowest 1 bit; all ones
                                 # for a zero source
if not nf:                       # NF=1 (APX) leaves the flags as they were
    cf = s == 0
    sf = msb(r)
    zf = 0                       # the result is never zero
    of = 0
    af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLSMSK, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI1 instructions

• ANDN
• BEXTR
• BLSI
• BLSR
• TZCNT

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions