BLSR

BLSR clears the lowest set bit of its source: for 0x28 it gives 0x20. It is the C idiom x & (x - 1) in one instruction, and with -mbmi or -march=x86-64-v3 GCC 14 and Clang 23 at -O2 compile that idiom to blsr eax, edi. BLSI keeps the bit that BLSR clears.

Walking the set bits#

A loop over the set bits of a mask takes the index of the lowest one with TZCNT, handles it, and clears it with BLSR until the mask is 0. BLSR’s ZF then serves as the loop condition: it is set exactly when no bit is left, so the loop needs no separate TEST.

Power-of-two tests#

A nonzero x is a power of two when BLSR leaves 0. For x && !(x & (x - 1)), GCC 14 emits a TEST for the zero case, then BLSR and SETE; Clang 23 counts the bits with POPCNT and compares the count with 1.

CF and ZF#

Both vendors’ manuals describe BLSR as a subtraction of 1 followed by an AND and take CF from the subtraction: CF is set only for a zero source, which borrows. Zen 5 agreed in every recorded case. ZF is set when the result is 0, that is, when the source had at most one bit set; SF copies the result’s top bit, OF is cleared, and AF and PF are undefined. So after BLSR, ZF = 1 with CF = 0 means exactly one bit was set.

A false dependency on Zen 5#

AMD’s Zen 5 guide says that some versions of Zen 5 make BLSR, BLSI, BLSMSK and TZCNT wait for the old value of their destination register, and suggests zeroing the destination with an XOR first (Section 2.9.9). Its instruction table lists BLSR as one macro-op with a latency of one cycle.

BLSR belongs to BMI1, part of x86-64-v3; APX adds an EVEX form and one that leaves the flags unchanged (NF).

In the optimization guide

What the optimization guide says about BLSR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 5

• Integer execution: Some versions of Zen 5 make TZCNT, BLSI, BLSR and BLSMSK wait for the old value of their destination.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = src.read()
r = s & (s - 1)                  # the lowest 1 bit cleared
if not nf:                       # NF=1 (APX) leaves the flags as they were
    cf = s == 0
    sf = msb(r)
    zf = r == 0
    of = 0
    af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BLSR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI1 instructions

• ANDN
• BEXTR
• BLSI
• BLSMSK
• TZCNT

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions