Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of BNDLDX that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BNDLDX bnd, mib not in 64-bit mode BNDLDX_BND_MEMbnd32NP 0F 1A /rMPX
BNDLDX bnd, mib 64-bit mode only BNDLDX_BND_MEMbnd64NP 0F 1A /rMPX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Forms only in 64-bit mode
on = 0                           # CPUID: no MPX: a hint NOP
if cpuid_leaf(7, 0)[1] >> 14 & 1:
    cfg = bndcfgu if CPL == 3 else bndcfgs
    on = cr4 >> 18 & 1 and cfg & 1  # CR4.OSXSAVE, BNDCFGx.EN
if on and xcr0 >> 3 & 3 == 3:    # XCR0's BNDREGS, BNDCSR
    if bnd.number > 3:           # BND4 to BND15
        fault(UD)
    la = src.address             # where the pointer is
    w = 28                       # its bits 47 + MAWA to 20
    if CPL == 3:                 # pick the directory's entry
        r = cpuid_leaf(7, 0)
        w += r[2] >> 17 & 31     # MAWAU; MAWA is 0 below CPL 3
    i = la >> 20 & (1 << w) - 1
    bde = (cfg >> 12 << 12) + 8 * i
    if not canonical(bde):
        fault(GP, 0)
    bt = load(bde, 64)           # the entry: a table's address
    if not bt & 1:               # not valid: BNDSTATUS gets
        bound_fault(bde | 2)     # the entry's address, code 2
    i = la >> 3 & 0x1FFFF        # bits 19:3 pick the table's
    bte = (bt >> 3 << 3) + 32 * i  # entry, of 32 bytes
    if not canonical(bte):
        fault(GP, 0)
    lb = load(bte, 64)
    ub = load(bte + 8, 64)
    p = load(bte + 16, 64)       # the pointer it was stored for
    if p == index_reg(src):      # still the pointer's value:
        bnd.write(ub << 64 | lb)  # its bounds
    else:
        bnd.write(0)             # else bounds that allow all
# nothing is read at src's address; the scale is ignored, and
# RIP-relative addressing is refused (#UD). A fault on the
# table's entry may leave bnd partly written (the SDM)

Run on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no MPX.

Forms not in 64-bit mode
on = 0                           # CPUID: no MPX: a hint NOP
if cpuid_leaf(7, 0)[1] >> 14 & 1:
    cfg = bndcfgu if CPL == 3 else bndcfgs
    on = cr4 >> 18 & 1 and cfg & 1  # CR4.OSXSAVE, BNDCFGx.EN
if on and xcr0 >> 3 & 3 == 3:    # XCR0's BNDREGS, BNDCSR
    if bnd.number > 3:           # BND0 to BND3 only
        fault(UD)
    la = src.address             # where the pointer is
    i = la >> 12 & 0xFFFFF       # bits 31:12 pick the entry
    bde = (low(cfg, 32) >> 12 << 12) + 4 * i
    bt = load(bde, 32)           # the entry: a table's address
    if not bt & 1:               # not valid: BNDSTATUS gets
        bound_fault(bde | 2)     # the entry's address, code 2
    i = la >> 2 & 0x3FF          # bits 11:2 pick the table's
    bte = (bt >> 2 << 2) + 16 * i  # entry, of 16 bytes
    lb = load(bte, 32)
    ub = load(bte + 4, 32)
    p = load(bte + 8, 32)        # the pointer it was stored for
    if p == index_reg(src):      # still the pointer's value:
        bnd.write(ub << 64 | lb)  # its bounds, zero-extended
    else:
        bnd.write(0)             # else bounds that allow all
# the addresses are 32 bits and offsets into DS

Not run on a processor: the form does not exist in 64-bit mode, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
BNDLDX bnd, mib not in 64-bit mode
bndexplicitwrite
mibexplicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MPX

MPX
CPUID.(EAX=07H,ECX=0):EBX[14] MPX

Skylake, Comet Lake, Cannon Lake, Skylake-SP, Cascade Lake, Cooper Lake, Goldmont, Goldmont Plus, Tremont, Snow Ridge

More MPX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-94 (BNDLDX)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.