Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of BNDMK that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BNDMK bnd, m BNDMK_BND_AGENF3 0F 1B /rMPX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = 0                           # CPUID: no MPX: a hint NOP
if cpuid_leaf(7, 0)[1] >> 14 & 1:
    cfg = bndcfgu if CPL == 3 else bndcfgs
    on = cr4 >> 18 & 1 and cfg & 1  # CR4.OSXSAVE, BNDCFGx.EN
if on and xcr0 >> 3 & 3 == 3:    # XCR0's BNDREGS, BNDCSR
    if bnd.number > 3:           # BND4 to BND15
        fault(UD)
    a = src.address              # as LEA computes it; not read
    if not canonical(a):         # #SS(0) when the base register
        fault(GP, 0)             # is RSP or RBP
    ub = low(~a, 64)             # kept as its ones' complement
    bnd.write(ub << 64 | base_reg(src))
# the lower bound is the base register alone, 0 without one: BNDMK
# bnd0, [rax + rcx] makes the buffer RAX to RAX + RCX, ends
# included. RIP-relative addressing is refused (#UD). Outside
# 64-bit mode both bounds are 32 bits, zero-extended

Run on AMD Zen 5 (EPYC 9645): 1 case. It ran where CPUID reported no MPX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
BNDMK bnd, m
bndexplicitwrite
mexplicitaddress only

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
MPX

MPX
CPUID.(EAX=07H,ECX=0):EBX[14] MPX

Skylake, Comet Lake, Cannon Lake, Skylake-SP, Cascade Lake, Cooper Lake, Goldmont, Goldmont Plus, Tremont, Snow Ridge

More MPX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-97 (BNDMK)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.