BSR

BSR finds the highest set bit of its source and writes that bit’s index to the destination: for 0x28 it gives 5. For a nonzero x that index is the integer part of log2(x), one less than the number of bits x needs. Like BSF, it clears ZF when it finds a bit, and for a zero source sets ZF and leaves the destination unwritten; the other flags are undefined.

From C#

C has no log2 for integers, but the index is 31 minus the count of leading zeros, and GCC 14 and Clang 23 at -O2 use BSR for both:

• 31 - __builtin_clz(x) becomes a lone bsr eax, edi;
• __builtin_clz(x) becomes bsr eax, edi and xor eax, 31, the XOR being a cheap 31 minus for a value between 0 and 31;
• 32 - __builtin_clz(x), the bit width, becomes BSR and an addition of 1.

C leaves __builtin_clz(0) undefined, which matches BSR leaving the destination alone. For x ? __builtin_clz(x) : 32, Clang relies on that: it loads 63 into EAX, runs bsr eax, edi and XORs with 31, which turns the untouched 63 into 32. GCC tests x and branches instead. As on the BSF page, Intel’s manual warns that some older processors clear bits 63:32 of the destination when a 32-bit BSR finds nothing; Zen 5 kept them.

BSR is not LZCNT#

LZCNT is encoded as BSR with an F3 prefix, but unlike TZCNT and BSF it counts from the other side: it returns 31 minus BSR’s answer for a 32-bit operand. A processor without LZCNT ignores the prefix and returns the index instead of the count, so compilers do not emit rep bsr; they use BSR and the XOR unless allowed LZCNT. With -mlzcnt, Clang still compiles 31 - __builtin_clz(x) to a plain BSR, while GCC computes it as 31 minus an LZCNT.

Speed#

Intel’s optimization manual lists BSR among the instructions of the one “Slow Int” execution unit of Golden Cove, with MUL and SHLD (Table 2-4). The instruction table of AMD’s Zen 5 guide lists BSR as one macro-op with a latency of one cycle.

In the optimization guide

What the optimization guide says about BSR, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Integer execution: Port 1 alone runs the slower integer operations: multiplication, PDEP and PEXT, popcnt, bsr, crc32 and the double shifts with an immediate count, which LLVM’s models give a latency of three cycles and one per cycle.

Jaguar and Puma

• Integer execution: LZCNT and POPCNT take one cycle on either ALU and TZCNT two, while BSF and BSR are microcoded, of seven and eight macro-ops and 4 and 5 cycles, so the newer instructions are the better choice where the zero case allows.

Skylake to Cooper Lake

• Integer execution: Port 1 alone runs integer multiplication, PDEP and PEXT, popcnt, lzcnt, tzcnt, bsf, bsr and the double shifts, with a latency of three cycles and one a cycle in LLVM’s models, as on Golden Cove.

Zen and Zen+

• Integer execution: BSF and BSR are six macro-ops with a latency of three and four cycles, while LZCNT and POPCNT are one macro-op of one cycle and TZCNT two of two cycles. sources differ

Zen 2

• Integer execution: BSF and BSR are six macro-ops with a latency of three and four cycles, while LZCNT and POPCNT are one macro-op of one cycle and TZCNT two; LLVM’s model agrees.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = src.read()
if s == 0:
    zf = 1
    # dest is not written, as both manuals say; Intel's adds
    # that some older processors clear bits 63:32 of it at a
    # 32-bit operand size
else:
    zf = 0
    for i in range(OSIZE):
        if s >> i & 1:
            n = i                # the last 1 bit found is the highest
    dest.write(n)                # a 32-bit register: bits 63:32 cleared
of = sf = af = pf = cf = UNDEFINED

Operands

Flags

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BSR, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSWAP
• BT
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions