x86-64.net

Instruction

BSRINIT

ACE instruction that sets every byte of the block scale register to 7FH, the E8M0 encoding of a scale factor of 1.0.

Extensions
Forms
1 (1 VEX)
Data
Intel XED v2026.08.23

BSRINIT sets all 128 bytes of ACE’s block scale register to 7Fh. Each byte is an E8M0 scale, a bare exponent with a bias of 127, so 7Fh stands for 2^0, and every scale becomes 1.0. It takes no operands beyond the register itself, bsrinit with bsr0 implied, and it is the only ACE instruction that needs no AVX-512 state.

Scales of one

The MX outer products, such as TOP4MXHF8PS, multiply every sum by one scale of each source, picked from the register by their immediate. With all scales at 1.0 they compute plain FP8 outer products, which the ACE specification gives as the way to use them on FP8 data without block scales. The same state is what the register holds after reset, after a successful LDTILECFG and after TILERELEASE, which set the scales to 7Fh and not to zero; BSRINIT gives it back without reloading the tile configuration, which would also clear the tiles. BSRMOVF loads real scales.

Encoding and checks

The encoding is C4 E2 FB 49 C0: VEX opcode 49h in map 0F38 with the F2 prefix and W1, ModRM C0h. TILEZERO is the same opcode with W0, its tile number in ModRM.reg, which BSRINIT requires to be 000. Its exception class, ACE-E5, is the shortest of ACE’s: 64-bit mode, CR4.OSXSAVE, XCR0 bits 17, 18 and 20 for the tiles and the scales, a loaded tile configuration and VEX.vvvv of 1111b, or #UD, and bit 18 of IA32_XFD for #NM. Like every ACE instruction it also raises #UD under any palette but 2. Since it touches no vector register, the specification checks neither XCR0’s SSE and AVX bits nor CR0.TS.

In our builds

GNU as 2.44 and Clang 23 reject the mnemonic, and neither compiler has ACE’s _bsrinit() intrinsic; objdump 2.44 decodes those bytes as (bad). No processor at hand has ACE, so this site’s recorded cases include none of BSRINIT.

Forms

Every encoding of BSRINIT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BSRINIT BSR0 64-bit mode only BSRINIT_BSR0VEX.LZ.F2.0F38.W1 49 C0ACE v1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

on = xcr0 if cr4 >> 18 & 1 else 0    # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB:            # TILECFG, TILEDATA, SCALEDATA
    fault(UD)
if palette != 2:                     # ACE's palette alone
    fault(UD)
if xfd >> 18 & 1:                    # the OS keeps the tiles from
    fault(NM)                        # this thread
for i in range(128):
    bsr0.b[i] = 0x7F                 # every scale 2^0
# no AVX-512 state is read: XCR0's AVX bits and CR0.TS do not count

Not run on a processor: none of these processors has ACE.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
BSRINIT BSR0 64-bit mode only
BSR0explicitwrite

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
ACE-E5

Attributes

What else XED records about the forms. How to read.

All forms
may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None in XED’s chip model, which lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.