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Instruction

BSRMOVF

ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half.

Extensions
Forms
2 (2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of BSRMOVF that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BSRMOVF BSR0, zmm, zmm 64-bit mode only BSRMOVF_BSR0_ZMMu64_ZMMu64EVEX.512.NP.MAP6.W1 95 /0ACE v1
BSRMOVF BSR0, zmm, m512 64-bit mode only BSRMOVF_BSR0_ZMMu64_MEMu64EVEX.512.NP.MAP6.W1 95 /0ACE v1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
ACE_1

ACE v1
CPUID.(EAX=07H,ECX=1):ECX[11] ACE
CPUID.(EAX=1DH,ECX=2):EAX[7:0] ≥ 1 ACE version

None yet: XED lists these instructions only under its placeholder for future processors.

More ACE instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.