Instruction
BSRMOVF
ACE instruction that loads all 1024 bits of the block scale register from two ZMM sources, the first giving the upper half.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
BSRMOVF loads the whole of ACE’s 1024-bit block scale
register from two 512-bit sources: bsrmovf bsr0, zmm1, zmm2/m512. The
first source, a ZMM register in EVEX.vvvv, gives bits 1023:512, the A
scales for the rows of an outer product; the second, a ZMM register or
64 bytes of memory, gives bits 511:0, the B scales for its columns. It
only writes: BSRMOVH and BSRMOVL
read either half back or replace one, and BSRINIT sets
every scale to 1.0.
Which byte scales what
Each byte is an E8M0 scale, 2^(e - 127), with FFh standing for a NaN. A half holds 16 dwords, one for each element of a source vector, and the four bytes of dword s are element s’s scales in groups 0 to 3: group g of element s is byte 4s + g of the half. So the scales line up with the dwords of the data, where an outer product such as TOP4MXHF8PS keeps four FP8 values for element s in dword s of each source. Its immediate picks one group for A, in bits 1:0, and one for B, in bits 4:3, so one load holds four sets of scales for each side, and each outer product names the set it uses. A scale of FFh makes every sum it touches the indefinite NaN.
Encoding and checks
EVEX opcode 95h in map 6 with no prefix and W1, 512 bits only, ModRM.reg
000 for bsr0; BSRMOVH and BSRMOVL use the same
opcode with F2 and F3. There is no mask, broadcast or zeroing: EVEX.aaa,
b and z must be zero, and EVEX.R and R’ must leave the register number
at 0, under exception class ACE-E2. Like the outer products, it needs
64-bit mode, the tile, scale and AVX-512 state in XCR0 and a tile
configuration with palette 2, or raises #UD; CR0.TS or bit 18 of
IA32_XFD raises #NM. A memory source can raise #AC when alignment
checking is on at CPL 3 and the address is not aligned.
In our builds
GNU as 2.44 and Clang 23 reject the mnemonic, and neither compiler has
ACE’s _bsrmovf(a_scales, b_scales) intrinsic. No processor at hand has
ACE, so this site’s recorded cases include none of BSRMOVF.
Forms
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
on = xcr0 if cr4 >> 18 & 1 else 0 # XCR0, where CR4.OSXSAVE is set
if on >> 17 & 0xB != 0xB: # TILECFG, TILEDATA, SCALEDATA
fault(UD)
if on & 0xE6 != 0xE6: # AVX-512's state, AVX's and
fault(UD) # SSE's
if palette != 2: # ACE's palette alone
fault(UD)
if cr0 >> 3 & 1 or xfd >> 18 & 1: # CR0.TS, or the OS keeps the
fault(NM) # tiles from this thread
bsr0.write(zmm2 << 512 | src3) # A scales from zmm2, B from src3
Not run on a processor: none of these processors has ACE.
Operands
| Operand | Kind | Action |
|---|---|---|
BSRMOVF BSR0, zmm, zmm/m512 64-bit mode only | ||
BSR0 | explicit | write |
zmm | explicit | read |
zmm/m512 | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
ACE-E2
Attributes
What else XED records about the forms. How to read.
- All forms
- may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
ACE_1 | ACE v1 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
More ACE instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.