BSWAP

BSWAP reverses the order of the bytes in a 32- or 64-bit register. That converts a value between little-endian, the order in which x86 keeps integers in memory, and big-endian, the order of network protocols and many file formats. GCC 14 and Clang 23 at -O2 compile __builtin_bswap32 and __builtin_bswap64 to it, and find it in plain C too: a 32-bit value assembled from four bytes, most significant first, as in p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3], becomes a 4-byte load and bswap eax.

16 bits#

Both manuals leave BSWAP of a 16-bit register undefined and suggest an XCHG of its two bytes instead. On this site’s Zen 5, every 16-bit case recorded cleared the low 16 bits and kept bits 63:16. Compilers use neither: both compile __builtin_bswap16 to rol ax, 8, a ROL of the word by 8, which swaps its bytes.

Register only#

BSWAP has no memory operand: its register is coded in the low three bits of the opcode, 0F C8 to 0F CF, with REX.B reaching R8 to R15 and REX.W choosing 64 bits. The 32-bit form clears bits 63:32 like any 32-bit write, so bswap eax is not half of a 64-bit swap.

MOVBE swaps the bytes as part of a load or a store. With -march=x86-64-v3, a level that includes it, both compilers turn the big-endian load above into a single movbe eax, dword ptr [rdi].

For arrays, Intel’s optimization manual prefers PSHUFB with a constant pattern, which reverses four doublewords at once: about twice as fast as BSWAP on the Intel Core microarchitecture, by its account (Section 6.6.5).

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

v = dest.read()
if OSIZE == 16:
    dest.write(UNDEFINED)        # the manuals leave the result undefined;
                                 # Zen 5 writes 0 and keeps bits 63:16
else:
    r = 0
    for i in range(OSIZE // 8):
        r = r << 8 | (v >> 8 * i & 0xFF)   # the bytes in reverse order
    dest.write(r)                # a 32-bit register: bits 63:32 cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BSWAP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BT
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions