Instruction
BSWAP
Reverses the byte order of a 32- or 64-bit register, converting between little- and big-endian values; with a 16-bit register the result is undefined.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
BSWAP r16/32/64
BSWAP_GPRv | 0F C8+r | Base instruction set |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to BSWAP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_bswap
int _bswap(int __A) |
|
_bswap64
long long _bswap64(long long A) |
|
__bswapd
int __bswapd(int __A) |
|
__bswapq
long long __bswapq(long long __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I486REAL | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
More General-purpose instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.