BT

BT copies one bit of its first operand into CF, where JC, JNC, SETC, CMOVC or ADC can use it. BTS, BTR and BTC copy the bit the same way and then set, clear or flip it. Clang 23 at -O2 compiles if (x & (1ULL << n)) on a 64-bit x to bt rdi, rsi and a CMOVAE, and the test of a fixed bit 40 to bt rdi, 40, which spares it a 10-byte MOV of the mask. GCC 14 tests such bits with shifts and ANDs, but sets and clears bit n of a register with BTS and BTR.

How far the offset reaches#

On a register, the bit number is taken modulo the operand size, 16, 32 or 64, and an immediate does the same on memory, so it selects a bit within the operand itself.

A register offset on a memory operand is different. The address then marks only bit 0 of a bit string, and the offset is a signed number, not masked, that can select a bit far below or above it: up to 2^63 bits either way with a 64-bit offset. The processor reads the 2, 4 or 8 bytes, by operand size, that hold the bit. This site’s Zen 5 ran cases reaching 64 bytes below and above the address, so bt [rdi], rsi tests bit RSI of a whole array at RDI.

Cautions#

• The access is wider than the bit. It covers a word of the operand’s size around the bit, so near memory-mapped I/O, or at the edge of mapped memory, Intel’s and AMD’s manuals advise a MOV and a BT on the register instead.
• Speed. The instruction table that comes with AMD’s Zen 5 guide lists BT with a memory operand and a register offset as microcoded, while the register and immediate forms are single macro-ops. Neither compiler uses it at -O2: for (a[n / 64] >> (n % 64)) & 1, both load the word with a MOV, and Clang then runs bt rcx, rsi on the register.
• No LOCK. BT only reads, and a LOCK prefix raises #UD; the atomic test-and-modify forms are LOCK BTS, LOCK BTR and LOCK BTC.

BT leaves ZF as it was, so code cannot use the zero flag to learn the bit; the flags table shows the others.

In the optimization guide

What the optimization guide says about BT, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: Some instructions write only part of the flags: inc and dec leave the carry flag as it was, and bt leaves the zero flag.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = bit & (OSIZE - 1)            # the offset, modulo the operand size
cf = base >> n & 1
of = sf = af = pf = UNDEFINED    # ZF keeps its value

n = signed(bit)                  # not masked: bit n can lie far below
                                 # or above the operand
a = base.address + n // OSIZE * (OSIZE // 8)   # the OSIZE bits that
cf = load(a, OSIZE) >> n % OSIZE & 1           # hold it
of = sf = af = pf = UNDEFINED    # ZF keeps its value

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions