x86-64.net

Instruction

BT

Copies the bit that a register or immediate offset selects in a register or memory operand into CF; a register offset can reach beyond a memory operand.

Extensions
Forms
4 (4 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of BT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
BT m16/32/64, imm8 BT_MEMv_IMMb0F BA /4 ibBase instruction set
BT r16/32/64, imm8 BT_GPRv_IMMb0F BA /4 ibBase instruction set
BT m16/32/64, r16/32/64 BT_MEMv_GPRv0F A3 /rBase instruction set
BT r16/32/64, r16/32/64 BT_GPRv_GPRv0F A3 /rBase instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.